include/dt-bindings/clock/qcom,gcc-msm8909.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,gcc-msm8909.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/qcom,gcc-msm8909.h- Extension
.h- Size
- 6787 bytes
- Lines
- 219
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_8909_H
#define _DT_BINDINGS_CLK_QCOM_GCC_8909_H
/* PLLs */
#define GPLL0_EARLY 0
#define GPLL0 1
#define GPLL1 2
#define GPLL1_VOTE 3
#define GPLL2_EARLY 4
#define GPLL2 5
#define BIMC_PLL_EARLY 6
#define BIMC_PLL 7
/* RCGs */
#define APSS_AHB_CLK_SRC 8
#define BIMC_DDR_CLK_SRC 9
#define BIMC_GPU_CLK_SRC 10
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22
#define BLSP1_UART1_APPS_CLK_SRC 23
#define BLSP1_UART2_APPS_CLK_SRC 24
#define BYTE0_CLK_SRC 25
#define CAMSS_GP0_CLK_SRC 26
#define CAMSS_GP1_CLK_SRC 27
#define CAMSS_TOP_AHB_CLK_SRC 28
#define CODEC_DIGCODEC_CLK_SRC 29
#define CRYPTO_CLK_SRC 30
#define CSI0_CLK_SRC 31
#define CSI0PHYTIMER_CLK_SRC 32
#define CSI1_CLK_SRC 33
#define ESC0_CLK_SRC 34
#define GFX3D_CLK_SRC 35
#define GP1_CLK_SRC 36
#define GP2_CLK_SRC 37
#define GP3_CLK_SRC 38
#define MCLK0_CLK_SRC 39
#define MCLK1_CLK_SRC 40
#define MDP_CLK_SRC 41
#define PCLK0_CLK_SRC 42
#define PCNOC_BFDCD_CLK_SRC 43
#define PDM2_CLK_SRC 44
#define SDCC1_APPS_CLK_SRC 45
#define SDCC2_APPS_CLK_SRC 46
#define SYSTEM_NOC_BFDCD_CLK_SRC 47
#define ULTAUDIO_AHBFABRIC_CLK_SRC 48
#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 49
#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 50
#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 51
#define ULTAUDIO_XO_CLK_SRC 52
#define USB_HS_SYSTEM_CLK_SRC 53
#define VCODEC0_CLK_SRC 54
#define VFE0_CLK_SRC 55
#define VSYNC_CLK_SRC 56
/* Voteable Clocks */
#define GCC_APSS_TCU_CLK 57
#define GCC_BLSP1_AHB_CLK 58
#define GCC_BLSP1_SLEEP_CLK 59
#define GCC_BOOT_ROM_AHB_CLK 60
#define GCC_CRYPTO_CLK 61
#define GCC_CRYPTO_AHB_CLK 62
#define GCC_CRYPTO_AXI_CLK 63
#define GCC_GFX_TBU_CLK 64
#define GCC_GFX_TCU_CLK 65
#define GCC_GTCU_AHB_CLK 66
#define GCC_MDP_TBU_CLK 67
#define GCC_PRNG_AHB_CLK 68
#define GCC_SMMU_CFG_CLK 69
#define GCC_VENUS_TBU_CLK 70
#define GCC_VFE_TBU_CLK 71
/* Branches */
#define GCC_BIMC_GFX_CLK 72
#define GCC_BIMC_GPU_CLK 73
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 74
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 75
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 76
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 77
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 79
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.