include/dt-bindings/clock/qcom,gcc-msm8998.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,gcc-msm8998.h

File Facts

System: Linux kernel
Corpus path: include/dt-bindings/clock/qcom,gcc-msm8998.h
Extension: .h
Size: 11060 bytes
Lines: 317
Domain: Repository Root And Misc
Bucket: include
Inferred role: Repository Root And Misc: implementation source
Status: source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H

#define BLSP1_QUP1_I2C_APPS_CLK_SRC				0
#define BLSP1_QUP1_SPI_APPS_CLK_SRC				1
#define BLSP1_QUP2_I2C_APPS_CLK_SRC				2
#define BLSP1_QUP2_SPI_APPS_CLK_SRC				3
#define BLSP1_QUP3_I2C_APPS_CLK_SRC				4
#define BLSP1_QUP3_SPI_APPS_CLK_SRC				5
#define BLSP1_QUP4_I2C_APPS_CLK_SRC				6
#define BLSP1_QUP4_SPI_APPS_CLK_SRC				7
#define BLSP1_QUP5_I2C_APPS_CLK_SRC				8
#define BLSP1_QUP5_SPI_APPS_CLK_SRC				9
#define BLSP1_QUP6_I2C_APPS_CLK_SRC				10
#define BLSP1_QUP6_SPI_APPS_CLK_SRC				11
#define BLSP1_UART1_APPS_CLK_SRC				12
#define BLSP1_UART2_APPS_CLK_SRC				13
#define BLSP1_UART3_APPS_CLK_SRC				14
#define BLSP2_QUP1_I2C_APPS_CLK_SRC				15
#define BLSP2_QUP1_SPI_APPS_CLK_SRC				16
#define BLSP2_QUP2_I2C_APPS_CLK_SRC				17
#define BLSP2_QUP2_SPI_APPS_CLK_SRC				18
#define BLSP2_QUP3_I2C_APPS_CLK_SRC				19
#define BLSP2_QUP3_SPI_APPS_CLK_SRC				20
#define BLSP2_QUP4_I2C_APPS_CLK_SRC				21
#define BLSP2_QUP4_SPI_APPS_CLK_SRC				22
#define BLSP2_QUP5_I2C_APPS_CLK_SRC				23
#define BLSP2_QUP5_SPI_APPS_CLK_SRC				24
#define BLSP2_QUP6_I2C_APPS_CLK_SRC				25
#define BLSP2_QUP6_SPI_APPS_CLK_SRC				26
#define BLSP2_UART1_APPS_CLK_SRC				27
#define BLSP2_UART2_APPS_CLK_SRC				28
#define BLSP2_UART3_APPS_CLK_SRC				29
#define GCC_AGGRE1_NOC_XO_CLK					30
#define GCC_AGGRE1_UFS_AXI_CLK					31
#define GCC_AGGRE1_USB3_AXI_CLK					32
#define GCC_APSS_QDSS_TSCTR_DIV2_CLK				33
#define GCC_APSS_QDSS_TSCTR_DIV8_CLK				34
#define GCC_BIMC_HMSS_AXI_CLK					35
#define GCC_BIMC_MSS_Q6_AXI_CLK					36
#define GCC_BLSP1_AHB_CLK					37
#define GCC_BLSP1_QUP1_I2C_APPS_CLK				38
#define GCC_BLSP1_QUP1_SPI_APPS_CLK				39
#define GCC_BLSP1_QUP2_I2C_APPS_CLK				40
#define GCC_BLSP1_QUP2_SPI_APPS_CLK				41
#define GCC_BLSP1_QUP3_I2C_APPS_CLK				42
#define GCC_BLSP1_QUP3_SPI_APPS_CLK				43
#define GCC_BLSP1_QUP4_I2C_APPS_CLK				44
#define GCC_BLSP1_QUP4_SPI_APPS_CLK				45
#define GCC_BLSP1_QUP5_I2C_APPS_CLK				46
#define GCC_BLSP1_QUP5_SPI_APPS_CLK				47
#define GCC_BLSP1_QUP6_I2C_APPS_CLK				48
#define GCC_BLSP1_QUP6_SPI_APPS_CLK				49
#define GCC_BLSP1_SLEEP_CLK					50
#define GCC_BLSP1_UART1_APPS_CLK				51
#define GCC_BLSP1_UART2_APPS_CLK				52
#define GCC_BLSP1_UART3_APPS_CLK				53
#define GCC_BLSP2_AHB_CLK					54
#define GCC_BLSP2_QUP1_I2C_APPS_CLK				55
#define GCC_BLSP2_QUP1_SPI_APPS_CLK				56
#define GCC_BLSP2_QUP2_I2C_APPS_CLK				57
#define GCC_BLSP2_QUP2_SPI_APPS_CLK				58
#define GCC_BLSP2_QUP3_I2C_APPS_CLK				59
#define GCC_BLSP2_QUP3_SPI_APPS_CLK				60
#define GCC_BLSP2_QUP4_I2C_APPS_CLK				61
#define GCC_BLSP2_QUP4_SPI_APPS_CLK				62
#define GCC_BLSP2_QUP5_I2C_APPS_CLK				63
#define GCC_BLSP2_QUP5_SPI_APPS_CLK				64
#define GCC_BLSP2_QUP6_I2C_APPS_CLK				65
#define GCC_BLSP2_QUP6_SPI_APPS_CLK				66
#define GCC_BLSP2_SLEEP_CLK					67
#define GCC_BLSP2_UART1_APPS_CLK				68
#define GCC_BLSP2_UART2_APPS_CLK				69
#define GCC_BLSP2_UART3_APPS_CLK				70
#define GCC_CFG_NOC_USB3_AXI_CLK				71
#define GCC_GP1_CLK						72
#define GCC_GP2_CLK						73
#define GCC_GP3_CLK						74
#define GCC_GPU_BIMC_GFX_CLK					75
#define GCC_GPU_BIMC_GFX_SRC_CLK				76
#define GCC_GPU_CFG_AHB_CLK					77
#define GCC_GPU_SNOC_DVM_GFX_CLK				78
#define GCC_HMSS_AHB_CLK					79
#define GCC_HMSS_AT_CLK						80
#define GCC_HMSS_DVM_BUS_CLK					81
#define GCC_HMSS_RBCPR_CLK					82
#define GCC_HMSS_TRIG_CLK					83
#define GCC_LPASS_AT_CLK					84
#define GCC_LPASS_TRIG_CLK					85
#define GCC_MMSS_NOC_CFG_AHB_CLK				86

Annotation

Atlas domain: Repository Root And Misc / include.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.