include/dt-bindings/clock/qcom,gcc-sdm845.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,gcc-sdm845.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/qcom,gcc-sdm845.h
Extension
.h
Size
8976 bytes
Lines
248
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H

/* GCC clock registers */
#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0
#define GCC_AGGRE_UFS_CARD_AXI_CLK				1
#define GCC_AGGRE_UFS_PHY_AXI_CLK				2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
#define GCC_AGGRE_USB3_SEC_AXI_CLK				4
#define GCC_BOOT_ROM_AHB_CLK					5
#define GCC_CAMERA_AHB_CLK					6
#define GCC_CAMERA_AXI_CLK					7
#define GCC_CAMERA_XO_CLK					8
#define GCC_CE1_AHB_CLK						9
#define GCC_CE1_AXI_CLK						10
#define GCC_CE1_CLK						11
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				12
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				13
#define GCC_CPUSS_AHB_CLK					14
#define GCC_CPUSS_AHB_CLK_SRC					15
#define GCC_CPUSS_RBCPR_CLK					16
#define GCC_CPUSS_RBCPR_CLK_SRC					17
#define GCC_DDRSS_GPU_AXI_CLK					18
#define GCC_DISP_AHB_CLK					19
#define GCC_DISP_AXI_CLK					20
#define GCC_DISP_GPLL0_CLK_SRC					21
#define GCC_DISP_GPLL0_DIV_CLK_SRC				22
#define GCC_DISP_XO_CLK						23
#define GCC_GP1_CLK						24
#define GCC_GP1_CLK_SRC						25
#define GCC_GP2_CLK						26
#define GCC_GP2_CLK_SRC						27
#define GCC_GP3_CLK						28
#define GCC_GP3_CLK_SRC						29
#define GCC_GPU_CFG_AHB_CLK					30
#define GCC_GPU_GPLL0_CLK_SRC					31
#define GCC_GPU_GPLL0_DIV_CLK_SRC				32
#define GCC_GPU_MEMNOC_GFX_CLK					33
#define GCC_GPU_SNOC_DVM_GFX_CLK				34
#define GCC_MSS_AXIS2_CLK					35
#define GCC_MSS_CFG_AHB_CLK					36
#define GCC_MSS_GPLL0_DIV_CLK_SRC				37
#define GCC_MSS_MFAB_AXIS_CLK					38
#define GCC_MSS_Q6_MEMNOC_AXI_CLK				39
#define GCC_MSS_SNOC_AXI_CLK					40
#define GCC_PCIE_0_AUX_CLK					41
#define GCC_PCIE_0_AUX_CLK_SRC					42
#define GCC_PCIE_0_CFG_AHB_CLK					43
#define GCC_PCIE_0_CLKREF_CLK					44
#define GCC_PCIE_0_MSTR_AXI_CLK					45
#define GCC_PCIE_0_PIPE_CLK					46
#define GCC_PCIE_0_SLV_AXI_CLK					47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				48
#define GCC_PCIE_1_AUX_CLK					49
#define GCC_PCIE_1_AUX_CLK_SRC					50
#define GCC_PCIE_1_CFG_AHB_CLK					51
#define GCC_PCIE_1_CLKREF_CLK					52
#define GCC_PCIE_1_MSTR_AXI_CLK					53
#define GCC_PCIE_1_PIPE_CLK					54
#define GCC_PCIE_1_SLV_AXI_CLK					55
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				56
#define GCC_PCIE_PHY_AUX_CLK					57
#define GCC_PCIE_PHY_REFGEN_CLK					58
#define GCC_PCIE_PHY_REFGEN_CLK_SRC				59
#define GCC_PDM2_CLK						60
#define GCC_PDM2_CLK_SRC					61
#define GCC_PDM_AHB_CLK						62
#define GCC_PDM_XO4_CLK						63
#define GCC_PRNG_AHB_CLK					64
#define GCC_QMIP_CAMERA_AHB_CLK					65
#define GCC_QMIP_DISP_AHB_CLK					66
#define GCC_QMIP_VIDEO_AHB_CLK					67
#define GCC_QUPV3_WRAP0_S0_CLK					68
#define GCC_QUPV3_WRAP0_S0_CLK_SRC				69
#define GCC_QUPV3_WRAP0_S1_CLK					70
#define GCC_QUPV3_WRAP0_S1_CLK_SRC				71
#define GCC_QUPV3_WRAP0_S2_CLK					72
#define GCC_QUPV3_WRAP0_S2_CLK_SRC				73
#define GCC_QUPV3_WRAP0_S3_CLK					74
#define GCC_QUPV3_WRAP0_S3_CLK_SRC				75
#define GCC_QUPV3_WRAP0_S4_CLK					76
#define GCC_QUPV3_WRAP0_S4_CLK_SRC				77
#define GCC_QUPV3_WRAP0_S5_CLK					78
#define GCC_QUPV3_WRAP0_S5_CLK_SRC				79
#define GCC_QUPV3_WRAP0_S6_CLK					80
#define GCC_QUPV3_WRAP0_S6_CLK_SRC				81
#define GCC_QUPV3_WRAP0_S7_CLK					82
#define GCC_QUPV3_WRAP0_S7_CLK_SRC				83
#define GCC_QUPV3_WRAP1_S0_CLK					84
#define GCC_QUPV3_WRAP1_S0_CLK_SRC				85

Annotation

Implementation Notes