include/dt-bindings/clock/qcom,gcc-sm8350.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,gcc-sm8350.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/qcom,gcc-sm8350.h
Extension
.h
Size
10081 bytes
Lines
266
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H

/* GCC HW clocks */
#define PCIE_0_PIPE_CLK						1
#define PCIE_1_PIPE_CLK						2
#define UFS_CARD_RX_SYMBOL_0_CLK				3
#define UFS_CARD_RX_SYMBOL_1_CLK				4
#define UFS_CARD_TX_SYMBOL_0_CLK				5
#define UFS_PHY_RX_SYMBOL_0_CLK					6
#define UFS_PHY_RX_SYMBOL_1_CLK					7
#define UFS_PHY_TX_SYMBOL_0_CLK					8
#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK			9
#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK			10

/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK				11
#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK				12
#define GCC_AGGRE_NOC_PCIE_TBU_CLK				13
#define GCC_AGGRE_UFS_CARD_AXI_CLK				14
#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			15
#define GCC_AGGRE_UFS_PHY_AXI_CLK				16
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			17
#define GCC_AGGRE_USB3_PRIM_AXI_CLK				18
#define GCC_AGGRE_USB3_SEC_AXI_CLK				19
#define GCC_BOOT_ROM_AHB_CLK					20
#define GCC_CAMERA_HF_AXI_CLK					21
#define GCC_CAMERA_SF_AXI_CLK					22
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				23
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				24
#define GCC_DDRSS_GPU_AXI_CLK					25
#define GCC_DDRSS_PCIE_SF_TBU_CLK				26
#define GCC_DISP_HF_AXI_CLK					27
#define GCC_DISP_SF_AXI_CLK					28
#define GCC_GP1_CLK						29
#define GCC_GP1_CLK_SRC						30
#define GCC_GP2_CLK						31
#define GCC_GP2_CLK_SRC						32
#define GCC_GP3_CLK						33
#define GCC_GP3_CLK_SRC						34
#define GCC_GPLL0						35
#define GCC_GPLL0_OUT_EVEN					36
#define GCC_GPLL4						37
#define GCC_GPLL9						38
#define GCC_GPU_GPLL0_CLK_SRC					39
#define GCC_GPU_GPLL0_DIV_CLK_SRC				40
#define GCC_GPU_IREF_EN						41
#define GCC_GPU_MEMNOC_GFX_CLK					42
#define GCC_GPU_SNOC_DVM_GFX_CLK				43
#define GCC_PCIE0_PHY_RCHNG_CLK					44
#define GCC_PCIE1_PHY_RCHNG_CLK					45
#define GCC_PCIE_0_AUX_CLK					46
#define GCC_PCIE_0_AUX_CLK_SRC					47
#define GCC_PCIE_0_CFG_AHB_CLK					48
#define GCC_PCIE_0_CLKREF_EN					49
#define GCC_PCIE_0_MSTR_AXI_CLK					50
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				51
#define GCC_PCIE_0_PIPE_CLK					52
#define GCC_PCIE_0_PIPE_CLK_SRC					53
#define GCC_PCIE_0_SLV_AXI_CLK					54
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				55
#define GCC_PCIE_1_AUX_CLK					56
#define GCC_PCIE_1_AUX_CLK_SRC					57
#define GCC_PCIE_1_CFG_AHB_CLK					58
#define GCC_PCIE_1_CLKREF_EN					59
#define GCC_PCIE_1_MSTR_AXI_CLK					60
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				61
#define GCC_PCIE_1_PIPE_CLK					62
#define GCC_PCIE_1_PIPE_CLK_SRC					63
#define GCC_PCIE_1_SLV_AXI_CLK					64
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				65
#define GCC_PDM2_CLK						66
#define GCC_PDM2_CLK_SRC					67
#define GCC_PDM_AHB_CLK						68
#define GCC_PDM_XO4_CLK						69
#define GCC_QMIP_CAMERA_NRT_AHB_CLK				70
#define GCC_QMIP_CAMERA_RT_AHB_CLK				71
#define GCC_QMIP_DISP_AHB_CLK					72
#define GCC_QMIP_VIDEO_CVP_AHB_CLK				73
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				74
#define GCC_QUPV3_WRAP0_CORE_2X_CLK				75
#define GCC_QUPV3_WRAP0_CORE_CLK				76
#define GCC_QUPV3_WRAP0_S0_CLK					77
#define GCC_QUPV3_WRAP0_S0_CLK_SRC				78
#define GCC_QUPV3_WRAP0_S1_CLK					79
#define GCC_QUPV3_WRAP0_S1_CLK_SRC				80
#define GCC_QUPV3_WRAP0_S2_CLK					81
#define GCC_QUPV3_WRAP0_S2_CLK_SRC				82
#define GCC_QUPV3_WRAP0_S3_CLK					83
#define GCC_QUPV3_WRAP0_S3_CLK_SRC				84

Annotation

Implementation Notes