include/dt-bindings/clock/qcom,ipq5424-gcc.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,ipq5424-gcc.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/qcom,ipq5424-gcc.h- Extension
.h- Size
- 5403 bytes
- Lines
- 158
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
#define GPLL0 0
#define GPLL4 1
#define GPLL2 2
#define GPLL2_OUT_MAIN 3
#define GCC_SLEEP_CLK_SRC 4
#define GCC_USB0_EUD_AT_CLK 6
#define GCC_PCIE0_AXI_M_CLK_SRC 7
#define GCC_PCIE0_AXI_M_CLK 8
#define GCC_PCIE1_AXI_M_CLK_SRC 9
#define GCC_PCIE1_AXI_M_CLK 10
#define GCC_PCIE2_AXI_M_CLK_SRC 11
#define GCC_PCIE2_AXI_M_CLK 12
#define GCC_PCIE3_AXI_M_CLK_SRC 13
#define GCC_PCIE3_AXI_M_CLK 14
#define GCC_PCIE0_AXI_S_CLK_SRC 15
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 16
#define GCC_PCIE0_AXI_S_CLK 17
#define GCC_PCIE1_AXI_S_CLK_SRC 18
#define GCC_PCIE1_AXI_S_BRIDGE_CLK 19
#define GCC_PCIE1_AXI_S_CLK 20
#define GCC_PCIE2_AXI_S_CLK_SRC 21
#define GCC_PCIE2_AXI_S_BRIDGE_CLK 22
#define GCC_PCIE2_AXI_S_CLK 23
#define GCC_PCIE3_AXI_S_CLK_SRC 24
#define GCC_PCIE3_AXI_S_BRIDGE_CLK 25
#define GCC_PCIE3_AXI_S_CLK 26
#define GCC_PCIE0_PIPE_CLK_SRC 27
#define GCC_PCIE0_PIPE_CLK 28
#define GCC_PCIE1_PIPE_CLK_SRC 29
#define GCC_PCIE1_PIPE_CLK 30
#define GCC_PCIE2_PIPE_CLK_SRC 31
#define GCC_PCIE2_PIPE_CLK 32
#define GCC_PCIE3_PIPE_CLK_SRC 33
#define GCC_PCIE3_PIPE_CLK 34
#define GCC_PCIE_AUX_CLK_SRC 35
#define GCC_PCIE0_AUX_CLK 36
#define GCC_PCIE1_AUX_CLK 37
#define GCC_PCIE2_AUX_CLK 38
#define GCC_PCIE3_AUX_CLK 39
#define GCC_PCIE0_AHB_CLK 40
#define GCC_PCIE1_AHB_CLK 41
#define GCC_PCIE2_AHB_CLK 42
#define GCC_PCIE3_AHB_CLK 43
#define GCC_USB0_AUX_CLK_SRC 44
#define GCC_USB0_AUX_CLK 45
#define GCC_USB0_MASTER_CLK 46
#define GCC_USB0_MOCK_UTMI_CLK_SRC 47
#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 48
#define GCC_USB0_MOCK_UTMI_CLK 49
#define GCC_USB0_PIPE_CLK_SRC 50
#define GCC_USB0_PIPE_CLK 51
#define GCC_USB0_PHY_CFG_AHB_CLK 52
#define GCC_USB0_SLEEP_CLK 53
#define GCC_SDCC1_APPS_CLK_SRC 54
#define GCC_SDCC1_APPS_CLK 55
#define GCC_SDCC1_ICE_CORE_CLK_SRC 56
#define GCC_SDCC1_ICE_CORE_CLK 57
#define GCC_SDCC1_AHB_CLK 58
#define GCC_PCNOC_BFDCD_CLK_SRC 59
#define GCC_NSSCFG_CLK 60
#define GCC_NSSNOC_NSSCC_CLK 61
#define GCC_NSSCC_CLK 62
#define GCC_NSSNOC_PCNOC_1_CLK 63
#define GCC_QPIC_AHB_CLK 64
#define GCC_QPIC_CLK 65
#define GCC_MDIO_AHB_CLK 66
#define GCC_PRNG_AHB_CLK 67
#define GCC_UNIPHY0_AHB_CLK 68
#define GCC_UNIPHY1_AHB_CLK 69
#define GCC_UNIPHY2_AHB_CLK 70
#define GCC_CMN_12GPLL_AHB_CLK 71
#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 72
#define GCC_NSSNOC_SNOC_CLK 73
#define GCC_NSSNOC_SNOC_1_CLK 74
#define GCC_WCSS_AHB_CLK_SRC 75
#define GCC_QDSS_AT_CLK_SRC 76
#define GCC_NSSNOC_ATB_CLK 77
#define GCC_QDSS_AT_CLK 78
#define GCC_QDSS_TSCTR_CLK_SRC 79
#define GCC_NSS_TS_CLK 80
#define GCC_QPIC_IO_MACRO_CLK_SRC 81
#define GCC_QPIC_IO_MACRO_CLK 82
#define GCC_LPASS_AXIM_CLK_SRC 83
#define GCC_LPASS_CORE_AXIM_CLK 84
#define GCC_LPASS_SWAY_CLK_SRC 85
#define GCC_LPASS_SWAY_CLK 86
#define GCC_CNOC_LPASS_CFG_CLK 87
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.