include/dt-bindings/clock/qcom,ipq9650-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,ipq9650-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/qcom,ipq9650-gcc.h
Extension
.h
Size
6245 bytes
Lines
173
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H
#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H

#define GCC_ADSS_PWM_CLK					0
#define GCC_ADSS_PWM_CLK_SRC					1
#define GCC_ANOC_PCIE0_1LANE_M_CLK				2
#define GCC_ANOC_PCIE0_1LANE_S_CLK				3
#define GCC_ANOC_PCIE1_2LANE_M_CLK				4
#define GCC_ANOC_PCIE1_2LANE_S_CLK				5
#define GCC_ANOC_PCIE2_2LANE_M_CLK				6
#define GCC_ANOC_PCIE2_2LANE_S_CLK				7
#define GCC_ANOC_PCIE3_2LANE_M_CLK				8
#define GCC_ANOC_PCIE3_2LANE_S_CLK				9
#define GCC_ANOC_PCIE4_1LANE_M_CLK				10
#define GCC_ANOC_PCIE4_1LANE_S_CLK				11
#define GCC_CMN_12GPLL_AHB_CLK					12
#define GCC_CMN_12GPLL_APU_CLK					13
#define GCC_CMN_12GPLL_SYS_CLK					14
#define GCC_CMN_LDO_CLK						15
#define GCC_MDIO_AHB_CLK					16
#define GCC_NSSCC_CLK						17
#define GCC_NSSCFG_CLK						18
#define GCC_NSSNOC_ATB_CLK					19
#define GCC_NSSNOC_MEMNOC_1_CLK					20
#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC				21
#define GCC_NSSNOC_MEMNOC_CLK					22
#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC				23
#define GCC_NSSNOC_NSSCC_CLK					24
#define GCC_NSSNOC_PCNOC_1_CLK					25
#define GCC_NSSNOC_QOSGEN_REF_CLK				26
#define GCC_NSSNOC_SNOC_1_CLK					27
#define GCC_NSSNOC_SNOC_CLK					28
#define GCC_NSSNOC_TIMEOUT_REF_CLK				29
#define GCC_NSSNOC_XO_DCD_CLK					30
#define GCC_NSS_TS_CLK						31
#define GCC_NSS_TS_CLK_SRC					32
#define GCC_PCIE0_AHB_CLK					33
#define GCC_PCIE0_AUX_CLK					34
#define GCC_PCIE0_AXI_M_CLK					35
#define GCC_PCIE0_AXI_M_CLK_SRC					36
#define GCC_PCIE0_AXI_S_BRIDGE_CLK				37
#define GCC_PCIE0_AXI_S_CLK					38
#define GCC_PCIE0_AXI_S_CLK_SRC					39
#define GCC_PCIE0_PIPE_CLK					40
#define GCC_PCIE0_PIPE_CLK_SRC					41
#define GCC_PCIE0_RCHNG_CLK					42
#define GCC_PCIE0_RCHNG_CLK_SRC					43
#define GCC_PCIE1_AHB_CLK					44
#define GCC_PCIE1_AUX_CLK					45
#define GCC_PCIE1_AXI_M_CLK					46
#define GCC_PCIE1_AXI_M_CLK_SRC					47
#define GCC_PCIE1_AXI_S_BRIDGE_CLK				48
#define GCC_PCIE1_AXI_S_CLK					49
#define GCC_PCIE1_AXI_S_CLK_SRC					50
#define GCC_PCIE1_PIPE_CLK					51
#define GCC_PCIE1_PIPE_CLK_SRC					52
#define GCC_PCIE1_RCHNG_CLK					53
#define GCC_PCIE1_RCHNG_CLK_SRC					54
#define GCC_PCIE2_AHB_CLK					55
#define GCC_PCIE2_AUX_CLK					56
#define GCC_PCIE2_AXI_M_CLK					57
#define GCC_PCIE2_AXI_M_CLK_SRC					58
#define GCC_PCIE2_AXI_S_BRIDGE_CLK				59
#define GCC_PCIE2_AXI_S_CLK					60
#define GCC_PCIE2_AXI_S_CLK_SRC					61
#define GCC_PCIE2_PIPE_CLK					62
#define GCC_PCIE2_PIPE_CLK_SRC					63
#define GCC_PCIE2_RCHNG_CLK					64
#define GCC_PCIE2_RCHNG_CLK_SRC					65
#define GCC_PCIE3_AHB_CLK					66
#define GCC_PCIE3_AUX_CLK					67
#define GCC_PCIE3_AXI_M_CLK					68
#define GCC_PCIE3_AXI_M_CLK_SRC					69
#define GCC_PCIE3_AXI_S_BRIDGE_CLK				70
#define GCC_PCIE3_AXI_S_CLK					71
#define GCC_PCIE3_AXI_S_CLK_SRC					72
#define GCC_PCIE3_PIPE_CLK					73
#define GCC_PCIE3_PIPE_CLK_SRC					74
#define GCC_PCIE3_RCHNG_CLK					75
#define GCC_PCIE3_RCHNG_CLK_SRC					76
#define GCC_PCIE4_AHB_CLK					77
#define GCC_PCIE4_AUX_CLK					78
#define GCC_PCIE4_AXI_M_CLK					79
#define GCC_PCIE4_AXI_M_CLK_SRC					80
#define GCC_PCIE4_AXI_S_BRIDGE_CLK				81
#define GCC_PCIE4_AXI_S_CLK					82
#define GCC_PCIE4_AXI_S_CLK_SRC					83
#define GCC_PCIE4_PIPE_CLK					84
#define GCC_PCIE4_PIPE_CLK_SRC					85
#define GCC_PCIE4_RCHNG_CLK					86

Annotation

Implementation Notes