include/dt-bindings/clock/qcom,sdx75-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,sdx75-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/qcom,sdx75-gcc.h
Extension
.h
Size
6867 bytes
Lines
194
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H

/* GCC clocks */
#define GPLL0							0
#define GPLL0_OUT_EVEN						1
#define GPLL4							2
#define GPLL5							3
#define GPLL6							4
#define GPLL8							5
#define GCC_AHB_PCIE_LINK_CLK					6
#define GCC_BOOT_ROM_AHB_CLK					7
#define GCC_EEE_EMAC0_CLK					8
#define GCC_EEE_EMAC0_CLK_SRC					9
#define GCC_EEE_EMAC1_CLK					10
#define GCC_EEE_EMAC1_CLK_SRC					11
#define GCC_EMAC0_AXI_CLK					12
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK				13
#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC			14
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK				15
#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC			16
#define GCC_EMAC0_PHY_AUX_CLK					17
#define GCC_EMAC0_PHY_AUX_CLK_SRC				18
#define GCC_EMAC0_PTP_CLK					19
#define GCC_EMAC0_PTP_CLK_SRC					20
#define GCC_EMAC0_RGMII_CLK					21
#define GCC_EMAC0_RGMII_CLK_SRC					22
#define GCC_EMAC0_RPCS_RX_CLK					23
#define GCC_EMAC0_RPCS_TX_CLK					24
#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC				25
#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC				26
#define GCC_EMAC0_SLV_AHB_CLK					27
#define GCC_EMAC0_XGXS_RX_CLK					28
#define GCC_EMAC0_XGXS_TX_CLK					29
#define GCC_EMAC1_AXI_CLK					30
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK				31
#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC			32
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK				33
#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC			34
#define GCC_EMAC1_PHY_AUX_CLK					35
#define GCC_EMAC1_PHY_AUX_CLK_SRC				36
#define GCC_EMAC1_PTP_CLK					37
#define GCC_EMAC1_PTP_CLK_SRC					38
#define GCC_EMAC1_RGMII_CLK					39
#define GCC_EMAC1_RGMII_CLK_SRC					40
#define GCC_EMAC1_RPCS_RX_CLK					41
#define GCC_EMAC1_RPCS_TX_CLK					42
#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC				43
#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC				44
#define GCC_EMAC1_SLV_AHB_CLK					45
#define GCC_EMAC1_XGXS_RX_CLK					46
#define GCC_EMAC1_XGXS_TX_CLK					47
#define GCC_EMAC_0_CLKREF_EN					48
#define GCC_EMAC_1_CLKREF_EN					49
#define GCC_GP1_CLK						50
#define GCC_GP1_CLK_SRC						51
#define GCC_GP2_CLK						52
#define GCC_GP2_CLK_SRC						53
#define GCC_GP3_CLK						54
#define GCC_GP3_CLK_SRC						55
#define GCC_PCIE_0_CLKREF_EN					56
#define GCC_PCIE_1_AUX_CLK					57
#define GCC_PCIE_1_AUX_PHY_CLK_SRC				58
#define GCC_PCIE_1_CFG_AHB_CLK					59
#define GCC_PCIE_1_CLKREF_EN					60
#define GCC_PCIE_1_MSTR_AXI_CLK					61
#define GCC_PCIE_1_PHY_RCHNG_CLK				62
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				63
#define GCC_PCIE_1_PIPE_CLK					64
#define GCC_PCIE_1_PIPE_CLK_SRC					65
#define GCC_PCIE_1_PIPE_DIV2_CLK				66
#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC				67
#define GCC_PCIE_1_SLV_AXI_CLK					68
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				69
#define GCC_PCIE_2_AUX_CLK					70
#define GCC_PCIE_2_AUX_PHY_CLK_SRC				71
#define GCC_PCIE_2_CFG_AHB_CLK					72
#define GCC_PCIE_2_CLKREF_EN					73
#define GCC_PCIE_2_MSTR_AXI_CLK					74
#define GCC_PCIE_2_PHY_RCHNG_CLK				75
#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC				76
#define GCC_PCIE_2_PIPE_CLK					77
#define GCC_PCIE_2_PIPE_CLK_SRC					78
#define GCC_PCIE_2_PIPE_DIV2_CLK				79
#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC				80
#define GCC_PCIE_2_SLV_AXI_CLK					81
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK				82
#define GCC_PCIE_AUX_CLK					83
#define GCC_PCIE_AUX_CLK_SRC					84
#define GCC_PCIE_AUX_PHY_CLK_SRC				85

Annotation

Implementation Notes