include/dt-bindings/clock/qcom,sm7150-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,sm7150-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/qcom,sm7150-gcc.h
Extension
.h
Size
6644 bytes
Lines
187
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H

/* GCC clock registers */
#define GCC_GPLL0_MAIN_DIV_CDIV				0
#define GPLL0						1
#define GPLL0_OUT_EVEN					2
#define GPLL6						3
#define GPLL7						4
#define GCC_AGGRE_NOC_PCIE_TBU_CLK			5
#define GCC_AGGRE_UFS_PHY_AXI_CLK			6
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK		7
#define GCC_AGGRE_USB3_PRIM_AXI_CLK			8
#define GCC_APC_VS_CLK					9
#define GCC_BOOT_ROM_AHB_CLK				10
#define GCC_CAMERA_HF_AXI_CLK				11
#define GCC_CAMERA_SF_AXI_CLK				12
#define GCC_CE1_AHB_CLK					13
#define GCC_CE1_AXI_CLK					14
#define GCC_CE1_CLK					15
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK			16
#define GCC_CPUSS_AHB_CLK				17
#define GCC_CPUSS_AHB_CLK_SRC				18
#define GCC_CPUSS_RBCPR_CLK				19
#define GCC_CPUSS_RBCPR_CLK_SRC				20
#define GCC_DDRSS_GPU_AXI_CLK				21
#define GCC_DISP_GPLL0_CLK_SRC				22
#define GCC_DISP_GPLL0_DIV_CLK_SRC			23
#define GCC_DISP_HF_AXI_CLK				24
#define GCC_DISP_SF_AXI_CLK				25
#define GCC_GP1_CLK					26
#define GCC_GP1_CLK_SRC					27
#define GCC_GP2_CLK					28
#define GCC_GP2_CLK_SRC					29
#define GCC_GP3_CLK					30
#define GCC_GP3_CLK_SRC					31
#define GCC_GPU_GPLL0_CLK_SRC				32
#define GCC_GPU_GPLL0_DIV_CLK_SRC			33
#define GCC_GPU_MEMNOC_GFX_CLK				34
#define GCC_GPU_SNOC_DVM_GFX_CLK			35
#define GCC_GPU_VS_CLK					36
#define GCC_NPU_AXI_CLK					37
#define GCC_NPU_CFG_AHB_CLK				38
#define GCC_NPU_GPLL0_CLK_SRC				39
#define GCC_NPU_GPLL0_DIV_CLK_SRC			40
#define GCC_PCIE_0_AUX_CLK				41
#define GCC_PCIE_0_AUX_CLK_SRC				42
#define GCC_PCIE_0_CFG_AHB_CLK				43
#define GCC_PCIE_0_CLKREF_CLK				44
#define GCC_PCIE_0_MSTR_AXI_CLK				45
#define GCC_PCIE_0_PIPE_CLK				46
#define GCC_PCIE_0_SLV_AXI_CLK				47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK			48
#define GCC_PCIE_PHY_AUX_CLK				49
#define GCC_PCIE_PHY_REFGEN_CLK				50
#define GCC_PCIE_PHY_REFGEN_CLK_SRC			51
#define GCC_PDM2_CLK					52
#define GCC_PDM2_CLK_SRC				53
#define GCC_PDM_AHB_CLK					54
#define GCC_PDM_XO4_CLK					55
#define GCC_PRNG_AHB_CLK				56
#define GCC_QUPV3_WRAP0_CORE_2X_CLK			57
#define GCC_QUPV3_WRAP0_CORE_CLK			58
#define GCC_QUPV3_WRAP0_S0_CLK				59
#define GCC_QUPV3_WRAP0_S0_CLK_SRC			60
#define GCC_QUPV3_WRAP0_S1_CLK				61
#define GCC_QUPV3_WRAP0_S1_CLK_SRC			62
#define GCC_QUPV3_WRAP0_S2_CLK				63
#define GCC_QUPV3_WRAP0_S2_CLK_SRC			64
#define GCC_QUPV3_WRAP0_S3_CLK				65
#define GCC_QUPV3_WRAP0_S3_CLK_SRC			66
#define GCC_QUPV3_WRAP0_S4_CLK				67
#define GCC_QUPV3_WRAP0_S4_CLK_SRC			68
#define GCC_QUPV3_WRAP0_S5_CLK				69
#define GCC_QUPV3_WRAP0_S5_CLK_SRC			70
#define GCC_QUPV3_WRAP0_S6_CLK				71
#define GCC_QUPV3_WRAP0_S6_CLK_SRC			72
#define GCC_QUPV3_WRAP0_S7_CLK				73
#define GCC_QUPV3_WRAP0_S7_CLK_SRC			74
#define GCC_QUPV3_WRAP1_CORE_2X_CLK			75
#define GCC_QUPV3_WRAP1_CORE_CLK			76
#define GCC_QUPV3_WRAP1_S0_CLK				77
#define GCC_QUPV3_WRAP1_S0_CLK_SRC			78
#define GCC_QUPV3_WRAP1_S1_CLK				79
#define GCC_QUPV3_WRAP1_S1_CLK_SRC			80
#define GCC_QUPV3_WRAP1_S2_CLK				81
#define GCC_QUPV3_WRAP1_S2_CLK_SRC			82
#define GCC_QUPV3_WRAP1_S3_CLK				83
#define GCC_QUPV3_WRAP1_S3_CLK_SRC			84
#define GCC_QUPV3_WRAP1_S4_CLK				85

Annotation

Implementation Notes