include/dt-bindings/clock/r9a07g043-cpg.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/r9a07g043-cpg.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/r9a07g043-cpg.h
Extension
.h
Size
8028 bytes
Lines
204
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* R9A07G043 CPG Core Clocks */
#define R9A07G043_CLK_I			0
#define R9A07G043_CLK_I2		1
#define R9A07G043_CLK_S0		2
#define R9A07G043_CLK_SPI0		3
#define R9A07G043_CLK_SPI1		4
#define R9A07G043_CLK_SD0		5
#define R9A07G043_CLK_SD1		6
#define R9A07G043_CLK_M0		7
#define R9A07G043_CLK_M2		8	/* RZ/G2UL Only */
#define R9A07G043_CLK_M3		9	/* RZ/G2UL Only */
#define R9A07G043_CLK_HP		10
#define R9A07G043_CLK_TSU		11
#define R9A07G043_CLK_ZT		12
#define R9A07G043_CLK_P0		13
#define R9A07G043_CLK_P1		14
#define R9A07G043_CLK_P2		15
#define R9A07G043_CLK_AT		16	/* RZ/G2UL Only */
#define R9A07G043_OSCCLK		17
#define R9A07G043_CLK_P0_DIV2		18

/* R9A07G043 Module Clocks */
#define R9A07G043_CA55_SCLK		0	/* RZ/G2UL Only */
#define R9A07G043_CA55_PCLK		1	/* RZ/G2UL Only */
#define R9A07G043_CA55_ATCLK		2	/* RZ/G2UL Only */
#define R9A07G043_CA55_GICCLK		3	/* RZ/G2UL Only */
#define R9A07G043_CA55_PERICLK		4	/* RZ/G2UL Only */
#define R9A07G043_CA55_ACLK		5	/* RZ/G2UL Only */
#define R9A07G043_CA55_TSCLK		6	/* RZ/G2UL Only */
#define R9A07G043_GIC600_GICCLK		7	/* RZ/G2UL Only */
#define R9A07G043_IA55_CLK		8	/* RZ/G2UL Only */
#define R9A07G043_IA55_PCLK		9	/* RZ/G2UL Only */
#define R9A07G043_MHU_PCLK		10	/* RZ/G2UL Only */
#define R9A07G043_SYC_CNT_CLK		11
#define R9A07G043_DMAC_ACLK		12
#define R9A07G043_DMAC_PCLK		13
#define R9A07G043_OSTM0_PCLK		14
#define R9A07G043_OSTM1_PCLK		15
#define R9A07G043_OSTM2_PCLK		16
#define R9A07G043_MTU_X_MCK_MTU3	17
#define R9A07G043_POE3_CLKM_POE		18
#define R9A07G043_WDT0_PCLK		19
#define R9A07G043_WDT0_CLK		20
#define R9A07G043_WDT2_PCLK		21	/* RZ/G2UL Only */
#define R9A07G043_WDT2_CLK		22	/* RZ/G2UL Only */
#define R9A07G043_SPI_CLK2		23
#define R9A07G043_SPI_CLK		24
#define R9A07G043_SDHI0_IMCLK		25
#define R9A07G043_SDHI0_IMCLK2		26
#define R9A07G043_SDHI0_CLK_HS		27
#define R9A07G043_SDHI0_ACLK		28
#define R9A07G043_SDHI1_IMCLK		29
#define R9A07G043_SDHI1_IMCLK2		30
#define R9A07G043_SDHI1_CLK_HS		31
#define R9A07G043_SDHI1_ACLK		32
#define R9A07G043_ISU_ACLK		33	/* RZ/G2UL Only */
#define R9A07G043_ISU_PCLK		34	/* RZ/G2UL Only */
#define R9A07G043_CRU_SYSCLK		35	/* RZ/G2UL Only */
#define R9A07G043_CRU_VCLK		36	/* RZ/G2UL Only */
#define R9A07G043_CRU_PCLK		37	/* RZ/G2UL Only */
#define R9A07G043_CRU_ACLK		38	/* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_A		39	/* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_P		40	/* RZ/G2UL Only */
#define R9A07G043_LCDC_CLK_D		41	/* RZ/G2UL Only */
#define R9A07G043_SSI0_PCLK2		42
#define R9A07G043_SSI0_PCLK_SFR		43
#define R9A07G043_SSI1_PCLK2		44
#define R9A07G043_SSI1_PCLK_SFR		45
#define R9A07G043_SSI2_PCLK2		46
#define R9A07G043_SSI2_PCLK_SFR		47
#define R9A07G043_SSI3_PCLK2		48
#define R9A07G043_SSI3_PCLK_SFR		49
#define R9A07G043_SRC_CLKP		50	/* RZ/G2UL Only */
#define R9A07G043_USB_U2H0_HCLK		51
#define R9A07G043_USB_U2H1_HCLK		52
#define R9A07G043_USB_U2P_EXR_CPUCLK	53
#define R9A07G043_USB_PCLK		54
#define R9A07G043_ETH0_CLK_AXI		55
#define R9A07G043_ETH0_CLK_CHI		56
#define R9A07G043_ETH1_CLK_AXI		57
#define R9A07G043_ETH1_CLK_CHI		58
#define R9A07G043_I2C0_PCLK		59
#define R9A07G043_I2C1_PCLK		60
#define R9A07G043_I2C2_PCLK		61
#define R9A07G043_I2C3_PCLK		62

Annotation

Implementation Notes