include/dt-bindings/clock/r9a09g011-cpg.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/r9a09g011-cpg.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/r9a09g011-cpg.h- Extension
.h- Size
- 10602 bytes
- Lines
- 353
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
dt-bindings/clock/renesas-cpg-mssr.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* Module Clocks */
#define R9A09G011_SYS_CLK 0
#define R9A09G011_PFC_PCLK 1
#define R9A09G011_PMC_CORE_CLOCK 2
#define R9A09G011_GIC_CLK 3
#define R9A09G011_RAMA_ACLK 4
#define R9A09G011_ROMA_ACLK 5
#define R9A09G011_SEC_ACLK 6
#define R9A09G011_SEC_PCLK 7
#define R9A09G011_SEC_TCLK 8
#define R9A09G011_DMAA_ACLK 9
#define R9A09G011_TSU0_PCLK 10
#define R9A09G011_TSU1_PCLK 11
#define R9A09G011_CST_TRACECLK 12
#define R9A09G011_CST_SB_CLK 13
#define R9A09G011_CST_AHB_CLK 14
#define R9A09G011_CST_ATB_SB_CLK 15
#define R9A09G011_CST_TS_SB_CLK 16
#define R9A09G011_SDI0_ACLK 17
#define R9A09G011_SDI0_IMCLK 18
#define R9A09G011_SDI0_IMCLK2 19
#define R9A09G011_SDI0_CLK_HS 20
#define R9A09G011_SDI1_ACLK 21
#define R9A09G011_SDI1_IMCLK 22
#define R9A09G011_SDI1_IMCLK2 23
#define R9A09G011_SDI1_CLK_HS 24
#define R9A09G011_EMM_ACLK 25
#define R9A09G011_EMM_IMCLK 26
#define R9A09G011_EMM_IMCLK2 27
#define R9A09G011_EMM_CLK_HS 28
#define R9A09G011_NFI_ACLK 29
#define R9A09G011_NFI_NF_CLK 30
#define R9A09G011_PCI_ACLK 31
#define R9A09G011_PCI_CLK_PMU 32
#define R9A09G011_PCI_APB_CLK 33
#define R9A09G011_USB_ACLK_H 34
#define R9A09G011_USB_ACLK_P 35
#define R9A09G011_USB_PCLK 36
#define R9A09G011_ETH0_CLK_AXI 37
#define R9A09G011_ETH0_CLK_CHI 38
#define R9A09G011_ETH0_GPTP_EXT 39
#define R9A09G011_SDT_CLK 40
#define R9A09G011_SDT_CLKAPB 41
#define R9A09G011_SDT_CLK48 42
#define R9A09G011_GRP_CLK 43
#define R9A09G011_CIF_P0_CLK 44
#define R9A09G011_CIF_P1_CLK 45
#define R9A09G011_CIF_APB_CLK 46
#define R9A09G011_DCI_CLKAXI 47
#define R9A09G011_DCI_CLKAPB 48
#define R9A09G011_DCI_CLKDCI2 49
#define R9A09G011_HMI_PCLK 50
#define R9A09G011_LCI_PCLK 51
#define R9A09G011_LCI_ACLK 52
#define R9A09G011_LCI_VCLK 53
#define R9A09G011_LCI_LPCLK 54
#define R9A09G011_AUI_CLK 55
#define R9A09G011_AUI_CLKAXI 56
#define R9A09G011_AUI_CLKAPB 57
#define R9A09G011_AUMCLK 58
#define R9A09G011_GMCLK0 59
#define R9A09G011_GMCLK1 60
#define R9A09G011_MTR_CLK0 61
#define R9A09G011_MTR_CLK1 62
#define R9A09G011_MTR_CLKAPB 63
#define R9A09G011_GFT_CLK 64
#define R9A09G011_GFT_CLKAPB 65
#define R9A09G011_GFT_MCLK 66
#define R9A09G011_ATGA_CLK 67
#define R9A09G011_ATGA_CLKAPB 68
#define R9A09G011_ATGB_CLK 69
#define R9A09G011_ATGB_CLKAPB 70
#define R9A09G011_SYC_CNT_CLK 71
#define R9A09G011_CPERI_GRPA_PCLK 72
#define R9A09G011_TIM0_CLK 73
#define R9A09G011_TIM1_CLK 74
#define R9A09G011_TIM2_CLK 75
Annotation
- Immediate include surface: `dt-bindings/clock/renesas-cpg-mssr.h`.
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.