include/dt-bindings/clock/renesas,r9a08g046-cpg.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/renesas,r9a08g046-cpg.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/renesas,r9a08g046-cpg.h
Extension
.h
Size
11569 bytes
Lines
343
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* R9A08G046 CPG Core Clocks */
#define R9A08G046_CLK_I			0
#define R9A08G046_CLK_IC0		1
#define R9A08G046_CLK_IC1		2
#define R9A08G046_CLK_IC2		3
#define R9A08G046_CLK_IC3		4
#define R9A08G046_CLK_P0		5
#define R9A08G046_CLK_P1		6
#define R9A08G046_CLK_P2		7
#define R9A08G046_CLK_P3		8
#define R9A08G046_CLK_P4		9
#define R9A08G046_CLK_P5		10
#define R9A08G046_CLK_P6		11
#define R9A08G046_CLK_P7		12
#define R9A08G046_CLK_P8		13
#define R9A08G046_CLK_P9		14
#define R9A08G046_CLK_P10		15
#define R9A08G046_CLK_P13		16
#define R9A08G046_CLK_P14		17
#define R9A08G046_CLK_P15		18
#define R9A08G046_CLK_P16		19
#define R9A08G046_CLK_P17		20
#define R9A08G046_CLK_P18		21
#define R9A08G046_CLK_P19		22
#define R9A08G046_CLK_P20		23
#define R9A08G046_CLK_M0		24
#define R9A08G046_CLK_M1		25
#define R9A08G046_CLK_M2		26
#define R9A08G046_CLK_M3		27
#define R9A08G046_CLK_M4		28
#define R9A08G046_CLK_M5		29
#define R9A08G046_CLK_M6		30
#define R9A08G046_CLK_AT		31
#define R9A08G046_CLK_B			32
#define R9A08G046_CLK_ETHTX01		33
#define R9A08G046_CLK_ETHTX02		34
#define R9A08G046_CLK_ETHRX01		35
#define R9A08G046_CLK_ETHRX02		36
#define R9A08G046_CLK_ETHRM0		37
#define R9A08G046_CLK_ETHTX11		38
#define R9A08G046_CLK_ETHTX12		39
#define R9A08G046_CLK_ETHRX11		40
#define R9A08G046_CLK_ETHRX12		41
#define R9A08G046_CLK_ETHRM1		42
#define R9A08G046_CLK_G			43
#define R9A08G046_CLK_HP		44
#define R9A08G046_CLK_SD0		45
#define R9A08G046_CLK_SD1		46
#define R9A08G046_CLK_SD2		47
#define R9A08G046_CLK_SPI0		48
#define R9A08G046_CLK_SPI1		49
#define R9A08G046_CLK_S0		50
#define R9A08G046_CLK_SWD		51
#define R9A08G046_OSCCLK		52
#define R9A08G046_OSCCLK2		53
#define R9A08G046_MIPI_DSI_PLLCLK	54
#define R9A08G046_USB_SCLK		55

/* R9A08G046 Module Clocks */
#define R9A08G046_CA55_SCLK		0
#define R9A08G046_CA55_PCLK		1
#define R9A08G046_CA55_ATCLK		2
#define R9A08G046_CA55_GICCLK		3
#define R9A08G046_CA55_PERICLK		4
#define R9A08G046_CA55_ACLK		5
#define R9A08G046_CA55_TSCLK		6
#define R9A08G046_CA55_CORECLK0		7
#define R9A08G046_CA55_CORECLK1		8
#define R9A08G046_CA55_CORECLK2		9
#define R9A08G046_CA55_CORECLK3		10
#define R9A08G046_SRAM_ACPU_ACLK0	11
#define R9A08G046_SRAM_ACPU_ACLK1	12
#define R9A08G046_SRAM_ACPU_ACLK2	13
#define R9A08G046_GIC600_GICCLK		14
#define R9A08G046_IA55_CLK		15
#define R9A08G046_IA55_PCLK		16
#define R9A08G046_MHU_PCLK		17
#define R9A08G046_SYC_CNT_CLK		18
#define R9A08G046_DMAC_ACLK		19
#define R9A08G046_DMAC_PCLK		20
#define R9A08G046_OSTM0_PCLK		21
#define R9A08G046_OSTM1_PCLK		22
#define R9A08G046_OSTM2_PCLK		23
#define R9A08G046_MTU_X_MCK_MTU3	24
#define R9A08G046_POE3_CLKM_POE		25

Annotation

Implementation Notes