include/dt-bindings/clock/rk3568-cru.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/rk3568-cru.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/rk3568-cru.h
Extension
.h
Size
23735 bytes
Lines
932
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H

/* pmucru-clocks indices */

/* pmucru plls */
#define PLL_PPLL		1
#define PLL_HPLL		2

/* pmucru clocks */
#define XIN_OSC0_DIV		4
#define CLK_RTC_32K		5
#define CLK_PMU			6
#define CLK_I2C0		7
#define CLK_RTC32K_FRAC		8
#define CLK_UART0_DIV		9
#define CLK_UART0_FRAC		10
#define SCLK_UART0		11
#define DBCLK_GPIO0		12
#define CLK_PWM0		13
#define CLK_CAPTURE_PWM0_NDFT	14
#define CLK_PMUPVTM		15
#define CLK_CORE_PMUPVTM	16
#define CLK_REF24M		17
#define XIN_OSC0_USBPHY0_G	18
#define CLK_USBPHY0_REF		19
#define XIN_OSC0_USBPHY1_G	20
#define CLK_USBPHY1_REF		21
#define XIN_OSC0_MIPIDSIPHY0_G	22
#define CLK_MIPIDSIPHY0_REF	23
#define XIN_OSC0_MIPIDSIPHY1_G	24
#define CLK_MIPIDSIPHY1_REF	25
#define CLK_WIFI_DIV		26
#define CLK_WIFI_OSC0		27
#define CLK_WIFI		28
#define CLK_PCIEPHY0_DIV	29
#define CLK_PCIEPHY0_OSC0	30
#define CLK_PCIEPHY0_REF	31
#define CLK_PCIEPHY1_DIV	32
#define CLK_PCIEPHY1_OSC0	33
#define CLK_PCIEPHY1_REF	34
#define CLK_PCIEPHY2_DIV	35
#define CLK_PCIEPHY2_OSC0	36
#define CLK_PCIEPHY2_REF	37
#define CLK_PCIE30PHY_REF_M	38
#define CLK_PCIE30PHY_REF_N	39
#define CLK_HDMI_REF		40
#define XIN_OSC0_EDPPHY_G	41
#define PCLK_PDPMU		42
#define PCLK_PMU		43
#define PCLK_UART0		44
#define PCLK_I2C0		45
#define PCLK_GPIO0		46
#define PCLK_PMUPVTM		47
#define PCLK_PWM0		48
#define CLK_PDPMU		49
#define SCLK_32K_IOE		50

#define CLKPMU_NR_CLKS		(SCLK_32K_IOE + 1)

/* cru-clocks indices */

/* cru plls */
#define PLL_APLL		1
#define PLL_DPLL		2
#define PLL_CPLL		3
#define PLL_GPLL		4
#define PLL_VPLL		5
#define PLL_NPLL		6

/* cru clocks */
#define CPLL_333M		9
#define ARMCLK			10
#define USB480M			11
#define USB480M_PHY		12
#define ACLK_CORE_NIU2BUS	18
#define CLK_CORE_PVTM		19
#define CLK_CORE_PVTM_CORE	20
#define CLK_CORE_PVTPLL		21
#define CLK_GPU_SRC		22
#define CLK_GPU_PRE_NDFT	23
#define CLK_GPU_PRE_MUX		24
#define ACLK_GPU_PRE		25
#define PCLK_GPU_PRE		26
#define CLK_GPU			27
#define CLK_GPU_NP5		28
#define PCLK_GPU_PVTM		29
#define CLK_GPU_PVTM		30
#define CLK_GPU_PVTM_CORE	31
#define CLK_GPU_PVTPLL		32

Annotation

Implementation Notes