include/dt-bindings/clock/rockchip,rk3506-cru.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/rockchip,rk3506-cru.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/rockchip,rk3506-cru.h
Extension
.h
Size
7588 bytes
Lines
286
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H

/* cru plls */
#define PLL_GPLL			0
#define PLL_V0PLL			1
#define PLL_V1PLL			2

/* cru-clocks indices */
#define ARMCLK				3
#define CLK_DDR				4
#define XIN24M_GATE			5
#define CLK_GPLL_GATE			6
#define CLK_V0PLL_GATE			7
#define CLK_V1PLL_GATE			8
#define CLK_GPLL_DIV			9
#define CLK_GPLL_DIV_100M		10
#define CLK_V0PLL_DIV			11
#define CLK_V1PLL_DIV			12
#define CLK_INT_VOICE_MATRIX0		13
#define CLK_INT_VOICE_MATRIX1		14
#define CLK_INT_VOICE_MATRIX2		15
#define CLK_FRAC_UART_MATRIX0_MUX	16
#define CLK_FRAC_UART_MATRIX1_MUX	17
#define CLK_FRAC_VOICE_MATRIX0_MUX	18
#define CLK_FRAC_VOICE_MATRIX1_MUX	19
#define CLK_FRAC_COMMON_MATRIX0_MUX	20
#define CLK_FRAC_COMMON_MATRIX1_MUX	21
#define CLK_FRAC_COMMON_MATRIX2_MUX	22
#define CLK_FRAC_UART_MATRIX0		23
#define CLK_FRAC_UART_MATRIX1		24
#define CLK_FRAC_VOICE_MATRIX0		25
#define CLK_FRAC_VOICE_MATRIX1		26
#define CLK_FRAC_COMMON_MATRIX0		27
#define CLK_FRAC_COMMON_MATRIX1		28
#define CLK_FRAC_COMMON_MATRIX2		29
#define CLK_REF_USBPHY_TOP		30
#define CLK_REF_DPHY_TOP		31
#define ACLK_CORE_ROOT			32
#define PCLK_CORE_ROOT			33
#define PCLK_DBG			34
#define PCLK_CORE_GRF			35
#define PCLK_CORE_CRU			36
#define CLK_CORE_EMA_DETECT		37
#define CLK_REF_PVTPLL_CORE		38
#define PCLK_GPIO1			39
#define DBCLK_GPIO1			40
#define ACLK_CORE_PERI_ROOT		41
#define HCLK_CORE_PERI_ROOT		42
#define PCLK_CORE_PERI_ROOT		43
#define CLK_DSMC			44
#define ACLK_DSMC			45
#define PCLK_DSMC			46
#define CLK_FLEXBUS_TX			47
#define CLK_FLEXBUS_RX			48
#define ACLK_FLEXBUS			49
#define HCLK_FLEXBUS			50
#define ACLK_DSMC_SLV			51
#define HCLK_DSMC_SLV			52
#define ACLK_BUS_ROOT			53
#define HCLK_BUS_ROOT			54
#define PCLK_BUS_ROOT			55
#define ACLK_SYSRAM			56
#define HCLK_SYSRAM			57
#define ACLK_DMAC0			58
#define ACLK_DMAC1			59
#define HCLK_M0				60
#define PCLK_BUS_GRF			61
#define PCLK_TIMER			62
#define CLK_TIMER0_CH0			63
#define CLK_TIMER0_CH1			64
#define CLK_TIMER0_CH2			65
#define CLK_TIMER0_CH3			66
#define CLK_TIMER0_CH4			67
#define CLK_TIMER0_CH5			68
#define PCLK_WDT0			69
#define TCLK_WDT0			70
#define PCLK_WDT1			71
#define TCLK_WDT1			72
#define PCLK_MAILBOX			73
#define PCLK_INTMUX			74
#define PCLK_SPINLOCK			75
#define PCLK_DDRC			76
#define HCLK_DDRPHY			77
#define PCLK_DDRMON			78
#define CLK_DDRMON_OSC			79
#define PCLK_STDBY			80
#define HCLK_USBOTG0			81
#define HCLK_USBOTG0_PMU		82
#define CLK_USBOTG0_ADP			83

Annotation

Implementation Notes