include/dt-bindings/clock/rockchip,rk3528-cru.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/rockchip,rk3528-cru.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/rockchip,rk3528-cru.h
Extension
.h
Size
12507 bytes
Lines
460
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H

/* cru-clocks indices */
#define PLL_APLL			0
#define PLL_CPLL			1
#define PLL_GPLL			2
#define PLL_PPLL			3
#define PLL_DPLL			4
#define ARMCLK				5
#define XIN_OSC0_HALF			6
#define CLK_MATRIX_50M_SRC		7
#define CLK_MATRIX_100M_SRC		8
#define CLK_MATRIX_150M_SRC		9
#define CLK_MATRIX_200M_SRC		10
#define CLK_MATRIX_250M_SRC		11
#define CLK_MATRIX_300M_SRC		12
#define CLK_MATRIX_339M_SRC		13
#define CLK_MATRIX_400M_SRC		14
#define CLK_MATRIX_500M_SRC		15
#define CLK_MATRIX_600M_SRC		16
#define CLK_UART0_SRC			17
#define CLK_UART0_FRAC			18
#define SCLK_UART0			19
#define CLK_UART1_SRC			20
#define CLK_UART1_FRAC			21
#define SCLK_UART1			22
#define CLK_UART2_SRC			23
#define CLK_UART2_FRAC			24
#define SCLK_UART2			25
#define CLK_UART3_SRC			26
#define CLK_UART3_FRAC			27
#define SCLK_UART3			28
#define CLK_UART4_SRC			29
#define CLK_UART4_FRAC			30
#define SCLK_UART4			31
#define CLK_UART5_SRC			32
#define CLK_UART5_FRAC			33
#define SCLK_UART5			34
#define CLK_UART6_SRC			35
#define CLK_UART6_FRAC			36
#define SCLK_UART6			37
#define CLK_UART7_SRC			38
#define CLK_UART7_FRAC			39
#define SCLK_UART7			40
#define CLK_I2S0_2CH_SRC		41
#define CLK_I2S0_2CH_FRAC		42
#define MCLK_I2S0_2CH_SAI_SRC		43
#define CLK_I2S3_8CH_SRC		44
#define CLK_I2S3_8CH_FRAC		45
#define MCLK_I2S3_8CH_SAI_SRC		46
#define CLK_I2S1_8CH_SRC		47
#define CLK_I2S1_8CH_FRAC		48
#define MCLK_I2S1_8CH_SAI_SRC		49
#define CLK_I2S2_2CH_SRC		50
#define CLK_I2S2_2CH_FRAC		51
#define MCLK_I2S2_2CH_SAI_SRC		52
#define CLK_SPDIF_SRC			53
#define CLK_SPDIF_FRAC			54
#define MCLK_SPDIF_SRC			55
#define DCLK_VOP_SRC0			56
#define DCLK_VOP_SRC1			57
#define CLK_HSM				58
#define CLK_CORE_SRC_ACS		59
#define CLK_CORE_SRC_PVTMUX		60
#define CLK_CORE_SRC			61
#define CLK_CORE			62
#define ACLK_M_CORE_BIU			63
#define CLK_CORE_PVTPLL_SRC		64
#define PCLK_DBG			65
#define SWCLKTCK			66
#define CLK_SCANHS_CORE			67
#define CLK_SCANHS_ACLKM_CORE		68
#define CLK_SCANHS_PCLK_DBG		69
#define CLK_SCANHS_PCLK_CPU_BIU		70
#define PCLK_CPU_ROOT			71
#define PCLK_CORE_GRF			72
#define PCLK_DAPLITE_BIU		73
#define PCLK_CPU_BIU			74
#define CLK_REF_PVTPLL_CORE		75
#define ACLK_BUS_VOPGL_ROOT		76
#define ACLK_BUS_VOPGL_BIU		77
#define ACLK_BUS_H_ROOT			78
#define ACLK_BUS_H_BIU			79
#define ACLK_BUS_ROOT			80
#define HCLK_BUS_ROOT			81
#define PCLK_BUS_ROOT			82
#define ACLK_BUS_M_ROOT			83
#define ACLK_SYSMEM_BIU			84
#define CLK_TIMER_ROOT			85

Annotation

Implementation Notes