include/dt-bindings/clock/rockchip,rk3562-cru.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/rockchip,rk3562-cru.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/rockchip,rk3562-cru.h- Extension
.h- Size
- 10083 bytes
- Lines
- 380
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
/* cru-clocks indices */
/* cru plls */
#define PLL_DMPLL0 0
#define PLL_APLL 1
#define PLL_GPLL 2
#define PLL_VPLL 3
#define PLL_HPLL 4
#define PLL_CPLL 5
#define PLL_DPLL 6
#define PLL_DMPLL1 7
/* cru clocks */
#define ARMCLK 8
#define CLK_GPU 9
#define ACLK_RKNN 10
#define CLK_DDR 11
#define CLK_MATRIX_50M_SRC 12
#define CLK_MATRIX_100M_SRC 13
#define CLK_MATRIX_125M_SRC 14
#define CLK_MATRIX_200M_SRC 15
#define CLK_MATRIX_300M_SRC 16
#define ACLK_TOP 17
#define ACLK_TOP_VIO 18
#define CLK_CAM0_OUT2IO 19
#define CLK_CAM1_OUT2IO 20
#define CLK_CAM2_OUT2IO 21
#define CLK_CAM3_OUT2IO 22
#define ACLK_BUS 23
#define HCLK_BUS 24
#define PCLK_BUS 25
#define PCLK_I2C1 26
#define PCLK_I2C2 27
#define PCLK_I2C3 28
#define PCLK_I2C4 29
#define PCLK_I2C5 30
#define CLK_I2C 31
#define CLK_I2C1 32
#define CLK_I2C2 33
#define CLK_I2C3 34
#define CLK_I2C4 35
#define CLK_I2C5 36
#define DCLK_BUS_GPIO 37
#define DCLK_BUS_GPIO3 38
#define DCLK_BUS_GPIO4 39
#define PCLK_TIMER 40
#define CLK_TIMER0 41
#define CLK_TIMER1 42
#define CLK_TIMER2 43
#define CLK_TIMER3 44
#define CLK_TIMER4 45
#define CLK_TIMER5 46
#define PCLK_STIMER 47
#define CLK_STIMER0 48
#define CLK_STIMER1 49
#define PCLK_WDTNS 50
#define CLK_WDTNS 51
#define PCLK_GRF 52
#define PCLK_SGRF 53
#define PCLK_MAILBOX 54
#define PCLK_INTC 55
#define ACLK_BUS_GIC400 56
#define ACLK_BUS_SPINLOCK 57
#define ACLK_DCF 58
#define PCLK_DCF 59
#define FCLK_BUS_CM0_CORE 60
#define CLK_BUS_CM0_RTC 61
#define HCLK_ICACHE 62
#define HCLK_DCACHE 63
#define PCLK_TSADC 64
#define CLK_TSADC 65
#define CLK_TSADC_TSEN 66
#define PCLK_DFT2APB 67
#define CLK_SARADC_VCCIO156 68
#define PCLK_GMAC 69
#define ACLK_GMAC 70
#define CLK_GMAC_125M_CRU_I 71
#define CLK_GMAC_50M_CRU_I 72
#define CLK_GMAC_50M_O 73
#define CLK_GMAC_ETH_OUT2IO 74
#define PCLK_APB2ASB_VCCIO156 75
#define PCLK_TO_VCCIO156 76
#define PCLK_DSIPHY 77
#define PCLK_DSITX 78
#define PCLK_CPU_EMA_DET 79
#define PCLK_HASH 80
#define PCLK_TOPCRU 81
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.