include/dt-bindings/clock/rockchip,rk3576-cru.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/rockchip,rk3576-cru.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/rockchip,rk3576-cru.h- Extension
.h- Size
- 16506 bytes
- Lines
- 608
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
/* cru-clocks indices */
/* cru plls */
#define PLL_BPLL 0
#define PLL_LPLL 1
#define PLL_VPLL 2
#define PLL_AUPLL 3
#define PLL_CPLL 4
#define PLL_GPLL 5
#define PLL_PPLL 6
#define ARMCLK_L 7
#define ARMCLK_B 8
/* cru clocks */
#define CLK_CPLL_DIV20 9
#define CLK_CPLL_DIV10 10
#define CLK_GPLL_DIV8 11
#define CLK_GPLL_DIV6 12
#define CLK_CPLL_DIV4 13
#define CLK_GPLL_DIV4 14
#define CLK_SPLL_DIV2 15
#define CLK_GPLL_DIV3 16
#define CLK_CPLL_DIV2 17
#define CLK_GPLL_DIV2 18
#define CLK_SPLL_DIV1 19
#define PCLK_TOP_ROOT 20
#define ACLK_TOP 21
#define HCLK_TOP 22
#define CLK_AUDIO_FRAC_0 23
#define CLK_AUDIO_FRAC_1 24
#define CLK_AUDIO_FRAC_2 25
#define CLK_AUDIO_FRAC_3 26
#define CLK_UART_FRAC_0 27
#define CLK_UART_FRAC_1 28
#define CLK_UART_FRAC_2 29
#define CLK_UART1_SRC_TOP 30
#define CLK_AUDIO_INT_0 31
#define CLK_AUDIO_INT_1 32
#define CLK_AUDIO_INT_2 33
#define CLK_PDM0_SRC_TOP 34
#define CLK_PDM1_OUT 35
#define CLK_GMAC0_125M_SRC 36
#define CLK_GMAC1_125M_SRC 37
#define LCLK_ASRC_SRC_0 38
#define LCLK_ASRC_SRC_1 39
#define REF_CLK0_OUT_PLL 40
#define REF_CLK1_OUT_PLL 41
#define REF_CLK2_OUT_PLL 42
#define REFCLKO25M_GMAC0_OUT 43
#define REFCLKO25M_GMAC1_OUT 44
#define CLK_CIFOUT_OUT 45
#define CLK_GMAC0_RMII_CRU 46
#define CLK_GMAC1_RMII_CRU 47
#define CLK_OTPC_AUTO_RD_G 48
#define CLK_OTP_PHY_G 49
#define CLK_MIPI_CAMERAOUT_M0 50
#define CLK_MIPI_CAMERAOUT_M1 51
#define CLK_MIPI_CAMERAOUT_M2 52
#define MCLK_PDM0_SRC_TOP 53
#define HCLK_AUDIO_ROOT 54
#define HCLK_ASRC_2CH_0 55
#define HCLK_ASRC_2CH_1 56
#define HCLK_ASRC_4CH_0 57
#define HCLK_ASRC_4CH_1 58
#define CLK_ASRC_2CH_0 59
#define CLK_ASRC_2CH_1 60
#define CLK_ASRC_4CH_0 61
#define CLK_ASRC_4CH_1 62
#define MCLK_SAI0_8CH_SRC 63
#define MCLK_SAI0_8CH 64
#define HCLK_SAI0_8CH 65
#define HCLK_SPDIF_RX0 66
#define MCLK_SPDIF_RX0 67
#define HCLK_SPDIF_RX1 68
#define MCLK_SPDIF_RX1 69
#define MCLK_SAI1_8CH_SRC 70
#define MCLK_SAI1_8CH 71
#define HCLK_SAI1_8CH 72
#define MCLK_SAI2_2CH_SRC 73
#define MCLK_SAI2_2CH 74
#define HCLK_SAI2_2CH 75
#define MCLK_SAI3_2CH_SRC 76
#define MCLK_SAI3_2CH 77
#define HCLK_SAI3_2CH 78
#define MCLK_SAI4_2CH_SRC 79
#define MCLK_SAI4_2CH 80
#define HCLK_SAI4_2CH 81
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.