include/dt-bindings/clock/rockchip,rv1126b-cru.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/rockchip,rv1126b-cru.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/rockchip,rv1126b-cru.h
Extension
.h
Size
10746 bytes
Lines
393
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H

/* pll clocks */
#define PLL_GPLL				0
#define PLL_CPLL				1
#define PLL_AUPLL				2
#define ARMCLK					3
#define SCLK_DDR				4

/* clk (clocks) */
#define CLK_CPLL_DIV20				5
#define CLK_CPLL_DIV10				6
#define CLK_CPLL_DIV8				7
#define CLK_GPLL_DIV8				8
#define CLK_GPLL_DIV6				9
#define CLK_GPLL_DIV4				10
#define CLK_CPLL_DIV3				11
#define CLK_GPLL_DIV3				12
#define CLK_CPLL_DIV2				13
#define CLK_GPLL_DIV2				14
#define CLK_CM_FRAC0				15
#define CLK_CM_FRAC1				16
#define CLK_CM_FRAC2				17
#define CLK_UART_FRAC0				18
#define CLK_UART_FRAC1				19
#define CLK_AUDIO_FRAC0				20
#define CLK_AUDIO_FRAC1				21
#define CLK_AUDIO_INT0				22
#define CLK_AUDIO_INT1				23
#define SCLK_UART0_SRC				24
#define SCLK_UART1				25
#define SCLK_UART2				26
#define SCLK_UART3				27
#define SCLK_UART4				28
#define SCLK_UART5				29
#define SCLK_UART6				30
#define SCLK_UART7				31
#define MCLK_SAI0				32
#define MCLK_SAI1				33
#define MCLK_SAI2				34
#define MCLK_PDM				35
#define CLKOUT_PDM				36
#define MCLK_ASRC0				37
#define MCLK_ASRC1				38
#define MCLK_ASRC2				39
#define MCLK_ASRC3				40
#define CLK_ASRC0				41
#define CLK_ASRC1				42
#define CLK_CORE_PLL				43
#define CLK_NPU_PLL				44
#define CLK_VEPU_PLL				45
#define CLK_ISP_PLL				46
#define CLK_AISP_PLL				47
#define CLK_SARADC0_SRC				48
#define CLK_SARADC1_SRC				49
#define CLK_SARADC2_SRC				50
#define HCLK_NPU_ROOT				51
#define PCLK_NPU_ROOT				52
#define ACLK_VEPU_ROOT				53
#define HCLK_VEPU_ROOT				54
#define PCLK_VEPU_ROOT				55
#define CLK_CORE_RGA_SRC			56
#define ACLK_GMAC_ROOT				57
#define ACLK_VI_ROOT				58
#define HCLK_VI_ROOT				59
#define PCLK_VI_ROOT				60
#define DCLK_VICAP_ROOT				61
#define CLK_SYS_DSMC_ROOT			62
#define ACLK_VDO_ROOT				63
#define ACLK_RKVDEC_ROOT			64
#define HCLK_VDO_ROOT				65
#define PCLK_VDO_ROOT				66
#define DCLK_OOC_SRC				67
#define DCLK_VOP				68
#define DCLK_DECOM_SRC				69
#define PCLK_DDR_ROOT				70
#define ACLK_SYSMEM_SRC				71
#define ACLK_TOP_ROOT				72
#define ACLK_BUS_ROOT				73
#define HCLK_BUS_ROOT				74
#define PCLK_BUS_ROOT				75
#define CCLK_SDMMC0				76
#define CCLK_SDMMC1				77
#define CCLK_EMMC				78
#define SCLK_2X_FSPI0				79
#define CLK_GMAC_PTP_REF_SRC			80
#define CLK_GMAC_125M				81
#define CLK_TIMER_ROOT				82
#define TCLK_WDT_NS_SRC				83

Annotation

Implementation Notes