include/dt-bindings/clock/spacemit,k1-syscon.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/spacemit,k1-syscon.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/spacemit,k1-syscon.h
Extension
.h
Size
9420 bytes
Lines
395
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
#define _DT_BINDINGS_SPACEMIT_CCU_H_

/* APBS (PLL) clocks */
#define CLK_PLL1		0
#define CLK_PLL2		1
#define CLK_PLL3		2
#define CLK_PLL1_D2		3
#define CLK_PLL1_D3		4
#define CLK_PLL1_D4		5
#define CLK_PLL1_D5		6
#define CLK_PLL1_D6		7
#define CLK_PLL1_D7		8
#define CLK_PLL1_D8		9
#define CLK_PLL1_D11		10
#define CLK_PLL1_D13		11
#define CLK_PLL1_D23		12
#define CLK_PLL1_D64		13
#define CLK_PLL1_D10_AUD	14
#define CLK_PLL1_D100_AUD	15
#define CLK_PLL2_D1		16
#define CLK_PLL2_D2		17
#define CLK_PLL2_D3		18
#define CLK_PLL2_D4		19
#define CLK_PLL2_D5		20
#define CLK_PLL2_D6		21
#define CLK_PLL2_D7		22
#define CLK_PLL2_D8		23
#define CLK_PLL3_D1		24
#define CLK_PLL3_D2		25
#define CLK_PLL3_D3		26
#define CLK_PLL3_D4		27
#define CLK_PLL3_D5		28
#define CLK_PLL3_D6		29
#define CLK_PLL3_D7		30
#define CLK_PLL3_D8		31
#define CLK_PLL3_80		32
#define CLK_PLL3_40		33
#define CLK_PLL3_20		34

/* MPMU clocks */
#define CLK_PLL1_307P2		0
#define CLK_PLL1_76P8		1
#define CLK_PLL1_61P44		2
#define CLK_PLL1_153P6		3
#define CLK_PLL1_102P4		4
#define CLK_PLL1_51P2		5
#define CLK_PLL1_51P2_AP	6
#define CLK_PLL1_57P6		7
#define CLK_PLL1_25P6		8
#define CLK_PLL1_12P8		9
#define CLK_PLL1_12P8_WDT	10
#define CLK_PLL1_6P4		11
#define CLK_PLL1_3P2		12
#define CLK_PLL1_1P6		13
#define CLK_PLL1_0P8		14
#define CLK_PLL1_409P6		15
#define CLK_PLL1_204P8		16
#define CLK_PLL1_491		17
#define CLK_PLL1_245P76		18
#define CLK_PLL1_614		19
#define CLK_PLL1_47P26		20
#define CLK_PLL1_31P5		21
#define CLK_PLL1_819		22
#define CLK_PLL1_1228		23
#define CLK_SLOW_UART		24
#define CLK_SLOW_UART1		25
#define CLK_SLOW_UART2		26
#define CLK_WDT			27
#define CLK_RIPC		28
#define CLK_I2S_SYSCLK		29
#define CLK_I2S_BCLK		30
#define CLK_APB			31
#define CLK_WDT_BUS		32
#define CLK_I2S_153P6		33
#define CLK_I2S_153P6_BASE	34
#define CLK_I2S_SYSCLK_SRC	35
#define CLK_I2S_BCLK_FACTOR	36

/* MPMU resets */
#define RESET_WDT		0

/* APBC clocks */
#define CLK_UART0		0
#define CLK_UART2		1
#define CLK_UART3		2
#define CLK_UART4		3
#define CLK_UART5		4
#define CLK_UART6		5
#define CLK_UART7		6

Annotation

Implementation Notes