include/dt-bindings/clock/sprd,sc9860-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/sprd,sc9860-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/sprd,sc9860-clk.h
Extension
.h
Size
10686 bytes
Lines
424
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Spreadtrum SC9860 platform clocks
//
// Copyright (C) 2017, Spreadtrum Communications Inc.

#ifndef _DT_BINDINGS_CLK_SC9860_H_
#define _DT_BINDINGS_CLK_SC9860_H_

#define	CLK_FAC_4M		0
#define	CLK_FAC_2M		1
#define	CLK_FAC_1M		2
#define	CLK_FAC_250K		3
#define	CLK_FAC_RPLL0_26M	4
#define	CLK_FAC_RPLL1_26M	5
#define	CLK_FAC_RCO25M		6
#define	CLK_FAC_RCO4M		7
#define	CLK_FAC_RCO2M		8
#define	CLK_FAC_3K2		9
#define	CLK_FAC_1K		10
#define	CLK_MPLL0_GATE		11
#define	CLK_MPLL1_GATE		12
#define	CLK_DPLL0_GATE		13
#define	CLK_DPLL1_GATE		14
#define	CLK_LTEPLL0_GATE	15
#define	CLK_TWPLL_GATE		16
#define	CLK_LTEPLL1_GATE	17
#define	CLK_RPLL0_GATE		18
#define	CLK_RPLL1_GATE		19
#define	CLK_CPPLL_GATE		20
#define	CLK_GPLL_GATE		21
#define CLK_PMU_GATE_NUM	(CLK_GPLL_GATE + 1)

#define	CLK_MPLL0		0
#define	CLK_MPLL1		1
#define	CLK_DPLL0		2
#define	CLK_DPLL1		3
#define	CLK_RPLL0		4
#define	CLK_RPLL1		5
#define	CLK_TWPLL		6
#define	CLK_LTEPLL0		7
#define	CLK_LTEPLL1		8
#define	CLK_GPLL		9
#define	CLK_CPPLL		10
#define	CLK_GPLL_42M5		11
#define	CLK_TWPLL_768M		12
#define	CLK_TWPLL_384M		13
#define	CLK_TWPLL_192M		14
#define	CLK_TWPLL_96M		15
#define	CLK_TWPLL_48M		16
#define	CLK_TWPLL_24M		17
#define	CLK_TWPLL_12M		18
#define	CLK_TWPLL_512M		19
#define	CLK_TWPLL_256M		20
#define	CLK_TWPLL_128M		21
#define	CLK_TWPLL_64M		22
#define	CLK_TWPLL_307M2		23
#define	CLK_TWPLL_153M6		24
#define	CLK_TWPLL_76M8		25
#define	CLK_TWPLL_51M2		26
#define	CLK_TWPLL_38M4		27
#define	CLK_TWPLL_19M2		28
#define	CLK_L0_614M4		29
#define	CLK_L0_409M6		30
#define	CLK_L0_38M		31
#define	CLK_L1_38M		32
#define	CLK_RPLL0_192M		33
#define	CLK_RPLL0_96M		34
#define	CLK_RPLL0_48M		35
#define	CLK_RPLL1_468M		36
#define	CLK_RPLL1_192M		37
#define	CLK_RPLL1_96M		38
#define	CLK_RPLL1_64M		39
#define	CLK_RPLL1_48M		40
#define	CLK_DPLL0_50M		41
#define	CLK_DPLL1_50M		42
#define	CLK_CPPLL_50M		43
#define	CLK_M0_39M		44
#define	CLK_M1_63M		45
#define CLK_PLL_NUM		(CLK_M1_63M + 1)


#define	CLK_AP_APB		0
#define	CLK_AP_USB3		1
#define	CLK_UART0		2
#define	CLK_UART1		3
#define	CLK_UART2		4
#define	CLK_UART3		5
#define	CLK_UART4		6
#define	CLK_I2C0		7

Annotation

Implementation Notes