include/dt-bindings/clock/sprd,sc9863a-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/sprd,sc9863a-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/sprd,sc9863a-clk.h
Extension
.h
Size
8384 bytes
Lines
340
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_SC9863A_H_
#define _DT_BINDINGS_CLK_SC9863A_H_

#define CLK_MPLL0_GATE		0
#define CLK_DPLL0_GATE		1
#define CLK_LPLL_GATE		2
#define CLK_GPLL_GATE		3
#define CLK_DPLL1_GATE		4
#define CLK_MPLL1_GATE		5
#define CLK_MPLL2_GATE		6
#define CLK_ISPPLL_GATE		7
#define CLK_PMU_APB_NUM		(CLK_ISPPLL_GATE + 1)

#define CLK_AUDIO_GATE		0
#define CLK_RPLL		1
#define CLK_RPLL_390M		2
#define CLK_RPLL_260M		3
#define CLK_RPLL_195M		4
#define CLK_RPLL_26M		5
#define CLK_ANLG_PHY_G5_NUM	(CLK_RPLL_26M + 1)

#define CLK_TWPLL		0
#define CLK_TWPLL_768M		1
#define CLK_TWPLL_384M		2
#define CLK_TWPLL_192M		3
#define CLK_TWPLL_96M		4
#define CLK_TWPLL_48M		5
#define CLK_TWPLL_24M		6
#define CLK_TWPLL_12M		7
#define CLK_TWPLL_512M		8
#define CLK_TWPLL_256M		9
#define CLK_TWPLL_128M		10
#define CLK_TWPLL_64M		11
#define CLK_TWPLL_307M2		12
#define CLK_TWPLL_219M4		13
#define CLK_TWPLL_170M6		14
#define CLK_TWPLL_153M6		15
#define CLK_TWPLL_76M8		16
#define CLK_TWPLL_51M2		17
#define CLK_TWPLL_38M4		18
#define CLK_TWPLL_19M2		19
#define CLK_LPLL		20
#define CLK_LPLL_409M6		21
#define CLK_LPLL_245M76		22
#define CLK_GPLL		23
#define CLK_ISPPLL		24
#define CLK_ISPPLL_468M		25
#define CLK_ANLG_PHY_G1_NUM	(CLK_ISPPLL_468M + 1)

#define CLK_DPLL0		0
#define CLK_DPLL1		1
#define CLK_DPLL0_933M		2
#define CLK_DPLL0_622M3		3
#define CLK_DPLL0_400M		4
#define CLK_DPLL0_266M7		5
#define CLK_DPLL0_123M1		6
#define CLK_DPLL0_50M		7
#define CLK_ANLG_PHY_G7_NUM	(CLK_DPLL0_50M + 1)

#define CLK_MPLL0		0
#define CLK_MPLL1		1
#define CLK_MPLL2		2
#define CLK_MPLL2_675M		3
#define CLK_ANLG_PHY_G4_NUM	(CLK_MPLL2_675M + 1)

#define CLK_AP_APB		0
#define CLK_AP_CE		1
#define CLK_NANDC_ECC		2
#define CLK_NANDC_26M		3
#define CLK_EMMC_32K		4
#define CLK_SDIO0_32K		5
#define CLK_SDIO1_32K		6
#define CLK_SDIO2_32K		7
#define CLK_OTG_UTMI		8
#define CLK_AP_UART0		9
#define CLK_AP_UART1		10
#define CLK_AP_UART2		11
#define CLK_AP_UART3		12
#define CLK_AP_UART4		13
#define CLK_AP_I2C0		14
#define CLK_AP_I2C1		15
#define CLK_AP_I2C2		16
#define CLK_AP_I2C3		17
#define CLK_AP_I2C4		18
#define CLK_AP_I2C5		19
#define CLK_AP_I2C6		20
#define CLK_AP_SPI0		21
#define CLK_AP_SPI1		22
#define CLK_AP_SPI2		23
#define CLK_AP_SPI3		24

Annotation

Implementation Notes