include/dt-bindings/clock/sprd,ums512-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/sprd,ums512-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/sprd,ums512-clk.h
Extension
.h
Size
10416 bytes
Lines
398
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_UMS512_H_
#define _DT_BINDINGS_CLK_UMS512_H_

#define CLK_26M_AUD			0
#define CLK_13M				1
#define CLK_6M5				2
#define CLK_4M3				3
#define CLK_2M				4
#define CLK_1M				5
#define CLK_250K			6
#define CLK_RCO_25M			7
#define CLK_RCO_4M			8
#define CLK_RCO_2M			9
#define CLK_ISPPLL_GATE			10
#define CLK_DPLL0_GATE			11
#define CLK_DPLL1_GATE			12
#define CLK_LPLL_GATE			13
#define CLK_TWPLL_GATE			14
#define CLK_GPLL_GATE			15
#define CLK_RPLL_GATE			16
#define CLK_CPPLL_GATE			17
#define CLK_MPLL0_GATE			18
#define CLK_MPLL1_GATE			19
#define CLK_MPLL2_GATE			20
#define CLK_PMU_GATE_NUM		(CLK_MPLL2_GATE + 1)

#define CLK_DPLL0			0
#define CLK_DPLL0_58M31			1
#define CLK_ANLG_PHY_G0_NUM		(CLK_DPLL0_58M31 + 1)

#define CLK_MPLL1			0
#define CLK_MPLL1_63M38			1
#define CLK_ANLG_PHY_G2_NUM		(CLK_MPLL1_63M38 + 1)

#define CLK_RPLL			0
#define CLK_AUDIO_GATE			1
#define CLK_MPLL0			2
#define CLK_MPLL0_56M88			3
#define CLK_MPLL2			4
#define CLK_MPLL2_47M13			5
#define CLK_ANLG_PHY_G3_NUM		(CLK_MPLL2_47M13 + 1)

#define CLK_TWPLL			0
#define CLK_TWPLL_768M			1
#define CLK_TWPLL_384M			2
#define CLK_TWPLL_192M			3
#define CLK_TWPLL_96M			4
#define CLK_TWPLL_48M			5
#define CLK_TWPLL_24M			6
#define CLK_TWPLL_12M			7
#define CLK_TWPLL_512M			8
#define CLK_TWPLL_256M			9
#define CLK_TWPLL_128M			10
#define CLK_TWPLL_64M			11
#define CLK_TWPLL_307M2			12
#define CLK_TWPLL_219M4			13
#define CLK_TWPLL_170M6			14
#define CLK_TWPLL_153M6			15
#define CLK_TWPLL_76M8			16
#define CLK_TWPLL_51M2			17
#define CLK_TWPLL_38M4			18
#define CLK_TWPLL_19M2			19
#define CLK_TWPLL_12M29			20
#define CLK_LPLL			21
#define CLK_LPLL_614M4			22
#define CLK_LPLL_409M6			23
#define CLK_LPLL_245M76			24
#define CLK_LPLL_30M72			25
#define CLK_ISPPLL			26
#define CLK_ISPPLL_468M			27
#define CLK_ISPPLL_78M			28
#define CLK_GPLL			29
#define CLK_GPLL_40M			30
#define CLK_CPPLL			31
#define CLK_CPPLL_39M32			32
#define CLK_ANLG_PHY_GC_NUM		(CLK_CPPLL_39M32 + 1)

#define CLK_AP_APB			0
#define CLK_IPI			        1
#define CLK_AP_UART0			2
#define CLK_AP_UART1			3
#define CLK_AP_UART2			4
#define CLK_AP_I2C0			5
#define CLK_AP_I2C1			6
#define CLK_AP_I2C2			7
#define CLK_AP_I2C3			8
#define CLK_AP_I2C4			9
#define CLK_AP_SPI0			10
#define CLK_AP_SPI1			11
#define CLK_AP_SPI2			12

Annotation

Implementation Notes