include/dt-bindings/clock/starfive-jh7100.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/starfive-jh7100.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/starfive-jh7100.h
Extension
.h
Size
6680 bytes
Lines
203
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__

#define JH7100_CLK_CPUNDBUS_ROOT	0
#define JH7100_CLK_DLA_ROOT		1
#define JH7100_CLK_DSP_ROOT		2
#define JH7100_CLK_GMACUSB_ROOT		3
#define JH7100_CLK_PERH0_ROOT		4
#define JH7100_CLK_PERH1_ROOT		5
#define JH7100_CLK_VIN_ROOT		6
#define JH7100_CLK_VOUT_ROOT		7
#define JH7100_CLK_AUDIO_ROOT		8
#define JH7100_CLK_CDECHIFI4_ROOT	9
#define JH7100_CLK_CDEC_ROOT		10
#define JH7100_CLK_VOUTBUS_ROOT		11
#define JH7100_CLK_CPUNBUS_ROOT_DIV	12
#define JH7100_CLK_DSP_ROOT_DIV		13
#define JH7100_CLK_PERH0_SRC		14
#define JH7100_CLK_PERH1_SRC		15
#define JH7100_CLK_PLL0_TESTOUT		16
#define JH7100_CLK_PLL1_TESTOUT		17
#define JH7100_CLK_PLL2_TESTOUT		18
#define JH7100_CLK_PLL2_REF		19
#define JH7100_CLK_CPU_CORE		20
#define JH7100_CLK_CPU_AXI		21
#define JH7100_CLK_AHB_BUS		22
#define JH7100_CLK_APB1_BUS		23
#define JH7100_CLK_APB2_BUS		24
#define JH7100_CLK_DOM3AHB_BUS		25
#define JH7100_CLK_DOM7AHB_BUS		26
#define JH7100_CLK_U74_CORE0		27
#define JH7100_CLK_U74_CORE1		28
#define JH7100_CLK_U74_AXI		29
#define JH7100_CLK_U74RTC_TOGGLE	30
#define JH7100_CLK_SGDMA2P_AXI		31
#define JH7100_CLK_DMA2PNOC_AXI		32
#define JH7100_CLK_SGDMA2P_AHB		33
#define JH7100_CLK_DLA_BUS		34
#define JH7100_CLK_DLA_AXI		35
#define JH7100_CLK_DLANOC_AXI		36
#define JH7100_CLK_DLA_APB		37
#define JH7100_CLK_VP6_CORE		38
#define JH7100_CLK_VP6BUS_SRC		39
#define JH7100_CLK_VP6_AXI		40
#define JH7100_CLK_VCDECBUS_SRC		41
#define JH7100_CLK_VDEC_BUS		42
#define JH7100_CLK_VDEC_AXI		43
#define JH7100_CLK_VDECBRG_MAIN		44
#define JH7100_CLK_VDEC_BCLK		45
#define JH7100_CLK_VDEC_CCLK		46
#define JH7100_CLK_VDEC_APB		47
#define JH7100_CLK_JPEG_AXI		48
#define JH7100_CLK_JPEG_CCLK		49
#define JH7100_CLK_JPEG_APB		50
#define JH7100_CLK_GC300_2X		51
#define JH7100_CLK_GC300_AHB		52
#define JH7100_CLK_JPCGC300_AXIBUS	53
#define JH7100_CLK_GC300_AXI		54
#define JH7100_CLK_JPCGC300_MAIN	55
#define JH7100_CLK_VENC_BUS		56
#define JH7100_CLK_VENC_AXI		57
#define JH7100_CLK_VENCBRG_MAIN		58
#define JH7100_CLK_VENC_BCLK		59
#define JH7100_CLK_VENC_CCLK		60
#define JH7100_CLK_VENC_APB		61
#define JH7100_CLK_DDRPLL_DIV2		62
#define JH7100_CLK_DDRPLL_DIV4		63
#define JH7100_CLK_DDRPLL_DIV8		64
#define JH7100_CLK_DDROSC_DIV2		65
#define JH7100_CLK_DDRC0		66
#define JH7100_CLK_DDRC1		67
#define JH7100_CLK_DDRPHY_APB		68
#define JH7100_CLK_NOC_ROB		69
#define JH7100_CLK_NOC_COG		70
#define JH7100_CLK_NNE_AHB		71
#define JH7100_CLK_NNEBUS_SRC1		72
#define JH7100_CLK_NNE_BUS		73
#define JH7100_CLK_NNE_AXI		74
#define JH7100_CLK_NNENOC_AXI		75
#define JH7100_CLK_DLASLV_AXI		76
#define JH7100_CLK_DSPX2C_AXI		77
#define JH7100_CLK_HIFI4_SRC		78
#define JH7100_CLK_HIFI4_COREFREE	79
#define JH7100_CLK_HIFI4_CORE		80
#define JH7100_CLK_HIFI4_BUS		81
#define JH7100_CLK_HIFI4_AXI		82
#define JH7100_CLK_HIFI4NOC_AXI		83
#define JH7100_CLK_SGDMA1P_BUS		84
#define JH7100_CLK_SGDMA1P_AXI		85
#define JH7100_CLK_DMA1P_AXI		86

Annotation

Implementation Notes