include/dt-bindings/gce/mt8195-gce.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/gce/mt8195-gce.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/gce/mt8195-gce.h- Extension
.h- Size
- 33996 bytes
- Lines
- 813
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_GCE_MT8195_H
#define _DT_BINDINGS_GCE_MT8195_H
/* assign timeout 0 also means default */
#define CMDQ_NO_TIMEOUT 0xffffffff
#define CMDQ_TIMEOUT_DEFAULT 1000
/* GCE thread priority */
#define CMDQ_THR_PRIO_LOWEST 0
#define CMDQ_THR_PRIO_1 1
#define CMDQ_THR_PRIO_2 2
#define CMDQ_THR_PRIO_3 3
#define CMDQ_THR_PRIO_4 4
#define CMDQ_THR_PRIO_5 5
#define CMDQ_THR_PRIO_6 6
#define CMDQ_THR_PRIO_HIGHEST 7
/* CPR count in 32bit register */
#define GCE_CPR_COUNT 1312
/* GCE subsys table */
#define SUBSYS_1400XXXX 0
#define SUBSYS_1401XXXX 1
#define SUBSYS_1402XXXX 2
#define SUBSYS_1c00XXXX 3
#define SUBSYS_1c01XXXX 4
#define SUBSYS_1c02XXXX 5
#define SUBSYS_1c10XXXX 6
#define SUBSYS_1c11XXXX 7
#define SUBSYS_1c12XXXX 8
#define SUBSYS_14f0XXXX 9
#define SUBSYS_14f1XXXX 10
#define SUBSYS_14f2XXXX 11
#define SUBSYS_1800XXXX 12
#define SUBSYS_1801XXXX 13
#define SUBSYS_1802XXXX 14
#define SUBSYS_1803XXXX 15
#define SUBSYS_1032XXXX 16
#define SUBSYS_1033XXXX 17
#define SUBSYS_1600XXXX 18
#define SUBSYS_1601XXXX 19
#define SUBSYS_14e0XXXX 20
#define SUBSYS_1c20XXXX 21
#define SUBSYS_1c30XXXX 22
#define SUBSYS_1c40XXXX 23
#define SUBSYS_1c50XXXX 24
#define SUBSYS_1c60XXXX 25
/* GCE General Purpose Register (GPR) support */
#define GCE_GPR_R00 0x0
#define GCE_GPR_R01 0x1
#define GCE_GPR_R02 0x2
#define GCE_GPR_R03 0x3
#define GCE_GPR_R04 0x4
#define GCE_GPR_R05 0x5
#define GCE_GPR_R06 0x6
#define GCE_GPR_R07 0x7
#define GCE_GPR_R08 0x8
#define GCE_GPR_R09 0x9
#define GCE_GPR_R10 0xa
#define GCE_GPR_R11 0xb
#define GCE_GPR_R12 0xc
#define GCE_GPR_R13 0xd
#define GCE_GPR_R14 0xe
#define GCE_GPR_R15 0xf
/* GCE hw event id */
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_0 1
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_1 2
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_2 3
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_3 4
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_4 5
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_5 6
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_6 7
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_7 8
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_8 9
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_9 10
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_10 11
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_11 12
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_12 13
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_13 14
#define CMDQ_EVENT_CQ_THR_DONE_TRAW0_14 15
#define CMDQ_EVENT_TRAW0_DMA_ERROR_INT 16
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_0 17
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_1 18
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_2 19
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_3 20
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_4 21
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_5 22
#define CMDQ_EVENT_CQ_THR_DONE_TRAW1_6 23
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.