include/dt-bindings/memory/mediatek,mt6893-memory-port.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/memory/mediatek,mt6893-memory-port.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/memory/mediatek,mt6893-memory-port.h
Extension
.h
Size
14483 bytes
Lines
289
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_MEMORY_MT6893_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT6893_LARB_PORT_H_

#include <dt-bindings/memory/mtk-memory-port.h>

/*
 * MM IOMMU supports 16GB dma address.
 *
 * The address will preassign like this:
 *
 * modules    dma-address-region	larbs-ports
 * disp         0 ~ 4G                  larb0/2
 * vcodec      4G ~ 8G                  larb4/5/7
 * cam/mdp     8G ~ 12G                 larb9/11/13/14/16/17/18/19/20
 * CCU0    0x4000_0000 ~ 0x43ff_ffff    larb13: port 9/10
 * CCU1    0x4400_0000 ~ 0x47ff_ffff    larb14: port 4/5
 *
 * larb3/6/8/10/12/15 are null.
 */

/* larb0 */
#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_DOM_ID(0, 0)
#define M4U_PORT_L0_MDP_RDMA4			MTK_M4U_DOM_ID(0, 1)
#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_DOM_ID(0, 2)
#define M4U_PORT_L0_OVL_2L_RDMA1_HDR		MTK_M4U_DOM_ID(0, 3)
#define M4U_PORT_L0_OVL_2L_RDMA3_HDR		MTK_M4U_DOM_ID(0, 4)
#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_DOM_ID(0, 5)
#define M4U_PORT_L0_OVL_2L_RDMA1		MTK_M4U_DOM_ID(0, 6)
#define M4U_PORT_L0_OVL_2L_RDMA3		MTK_M4U_DOM_ID(0, 7)
#define M4U_PORT_L0_OVL_RDMA1_SYSRAM		MTK_M4U_DOM_ID(0, 8)
#define M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM		MTK_M4U_DOM_ID(0, 9)
#define M4U_PORT_L0_OVL_2L_RDMA2_SYSRAM		MTK_M4U_DOM_ID(0, 10)
#define M4U_PORT_L0_DISP_WDMA0			MTK_M4U_DOM_ID(0, 11)
#define M4U_PORT_L0_DISP_RDMA0			MTK_M4U_DOM_ID(0, 12)
#define M4U_PORT_L0_DISP_UFBC_WDMA0		MTK_M4U_DOM_ID(0, 13)
#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_DOM_ID(0, 14)

/* larb1 */
#define M4U_PORT_L1_DISP_POSTMASK1		MTK_M4U_DOM_ID(1, 0)
#define M4U_PORT_L1_MDP_RDMA5			MTK_M4U_DOM_ID(1, 1)
#define M4U_PORT_L1_OVL_RDMA1_HDR		MTK_M4U_DOM_ID(1, 2)
#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_DOM_ID(1, 3)
#define M4U_PORT_L1_OVL_2L_RDMA2_HDR		MTK_M4U_DOM_ID(1, 4)
#define M4U_PORT_L1_OVL_RDMA1			MTK_M4U_DOM_ID(1, 5)
#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_DOM_ID(1, 6)
#define M4U_PORT_L1_OVL_2L_RDMA2		MTK_M4U_DOM_ID(1, 7)
#define M4U_PORT_L1_OVL_RDMA0_SYSRAM		MTK_M4U_DOM_ID(1, 8)
#define M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM		MTK_M4U_DOM_ID(1, 9)
#define M4U_PORT_L1_OVL_2L_RDMA3_SYSRAM		MTK_M4U_DOM_ID(1, 10)
#define M4U_PORT_L1_DISP_WDMA1			MTK_M4U_DOM_ID(1, 11)
#define M4U_PORT_L1_DISP_RDMA1			MTK_M4U_DOM_ID(1, 12)
#define M4U_PORT_L1_DISP_UFBC_WDMA1		MTK_M4U_DOM_ID(1, 13)
#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_DOM_ID(1, 14)

/* larb2 */
#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_DOM_ID(2, 0)
#define M4U_PORT_L2_MDP_RDMA2			MTK_M4U_DOM_ID(2, 1)
#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_DOM_ID(2, 2)
#define M4U_PORT_L2_MDP_WROT2			MTK_M4U_DOM_ID(2, 3)
#define M4U_PORT_L2_MDP_FILMGRAIN0		MTK_M4U_DOM_ID(2, 4)
#define M4U_PORT_L2_MDP_FAKE0			MTK_M4U_DOM_ID(2, 5)

/* larb3: null */

/* larb4 */
#define M4U_PORT_L4_VDEC_MC_EXT_MDP		MTK_M4U_DOM_ID(4, 0)
#define M4U_PORT_L4_VDEC_UFO_EXT_MDP		MTK_M4U_DOM_ID(4, 1)
#define M4U_PORT_L4_VDEC_PP_EXT_MDP		MTK_M4U_DOM_ID(4, 2)
#define M4U_PORT_L4_VDEC_PRED_RD_EXT_MDP	MTK_M4U_DOM_ID(4, 3)
#define M4U_PORT_L4_VDEC_PRED_WR_EXT_MDP	MTK_M4U_DOM_ID(4, 4)
#define M4U_PORT_L4_VDEC_PPWRAP_EXT_MDP		MTK_M4U_DOM_ID(4, 5)
#define M4U_PORT_L4_VDEC_TILE_EXT_MDP		MTK_M4U_DOM_ID(4, 6)
#define M4U_PORT_L4_VDEC_VLD_EXT_MDP		MTK_M4U_DOM_ID(4, 7)
#define M4U_PORT_L4_VDEC_VLD2_EXT_MDP		MTK_M4U_DOM_ID(4, 8)
#define M4U_PORT_L4_VDEC_AVC_MV_EXT_MDP		MTK_M4U_DOM_ID(4, 9)
#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT_MDP	MTK_M4U_DOM_ID(4, 10)

/* larb5 */
#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT_DISP	MTK_M4U_DOM_ID(5, 0)
#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT_DISP	MTK_M4U_DOM_ID(5, 1)
#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT_DISP	MTK_M4U_DOM_ID(5, 2)
#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT_DISP	MTK_M4U_DOM_ID(5, 3)
#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT_DISP	MTK_M4U_DOM_ID(5, 4)
#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT_DISP	MTK_M4U_DOM_ID(5, 5)
#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP MTK_M4U_DOM_ID(5, 6)
#define M4U_PORT_L5_VDEC_UFO_ENC_EXT_DISP	MTK_M4U_DOM_ID(5, 7)

/* larb6: null */

/* larb7 */

Annotation

Implementation Notes