include/dt-bindings/memory/mediatek,mt8188-memory-port.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/memory/mediatek,mt8188-memory-port.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/memory/mediatek,mt8188-memory-port.h
Extension
.h
Size
24961 bytes
Lines
490
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_

#include <dt-bindings/memory/mtk-memory-port.h>

/*
 * MM IOMMU larbs:
 * From below, for example larb11 has larb11a/larb11b/larb11c,
 * the index of larb is not in order. So we reindexed these larbs from a
 * software view.
 */
#define SMI_L0_ID		0
#define SMI_L1_ID		1
#define SMI_L2_ID		2
#define SMI_L3_ID		3
#define SMI_L4_ID		4
#define SMI_L5_ID		5
#define SMI_L6_ID		6
#define SMI_L7_ID		7
#define SMI_L9_ID		8
#define SMI_L10_ID		9
#define SMI_L11A_ID		10
#define SMI_L11B_ID		11
#define SMI_L11C_ID		12
#define SMI_L12_ID		13
#define SMI_L13_ID		14
#define SMI_L14_ID		15
#define SMI_L15_ID		16
#define SMI_L16A_ID		17
#define SMI_L16B_ID		18
#define SMI_L17A_ID		19
#define SMI_L17B_ID		20
#define SMI_L19_ID		21
#define SMI_L21_ID		22
#define SMI_L23_ID		23
#define SMI_L27_ID		24
#define SMI_L28_ID		25

/*
 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
 * locate in anyone region. BUT:
 * a) Make sure all the ports inside a larb are in one range.
 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
 *
 * This is the suggested mapping in this SoC:
 *
 * modules    dma-address-region	larbs-ports
 * disp         0 ~ 4G                  larb0/1/2/3
 * vcodec      4G ~ 8G                  larb19(21)[1]/21(22)/23
 * cam/mdp     8G ~ 12G                 the other larbs.
 * N/A         12G ~ 16G
 * CCU0   0x24000_0000 ~ 0x243ff_ffff   larb27(24): port 0/1
 * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb27(24): port 2/3
 *
 * This SoC have two MM IOMMU HWs, this is the connected information:
 * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21
 * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27
 *
 * [1]: This is larb19, but the index is 21 from the SW view.
 */

/* MM IOMMU ports */
/* LARB 0 -- VDO-0 */
#define M4U_PORT_L0_DISP_RDMA1			MTK_M4U_ID(SMI_L0_ID, 0)
#define M4U_PORT_L0_DISP_WDMA0			MTK_M4U_ID(SMI_L0_ID, 1)
#define M4U_PORT_L0_DISP_OVL0_RDMA0		MTK_M4U_ID(SMI_L0_ID, 2)
#define M4U_PORT_L0_DISP_OVL0_RDMA1		MTK_M4U_ID(SMI_L0_ID, 3)
#define M4U_PORT_L0_DISP_OVL0_HDR		MTK_M4U_ID(SMI_L0_ID, 4)
#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(SMI_L0_ID, 5)
#define M4U_PORT_L0_DISP_FAKE_ENG0		MTK_M4U_ID(SMI_L0_ID, 6)

/* LARB 1 -- VD0-0 */
#define M4U_PORT_L1_DISP_RDMA0			MTK_M4U_ID(SMI_L1_ID, 0)
#define M4U_PORT_L1_DISP_WDMA1			MTK_M4U_ID(SMI_L1_ID, 1)
#define M4U_PORT_L1_DISP_OVL1_RDMA0		MTK_M4U_ID(SMI_L1_ID, 2)
#define M4U_PORT_L1_DISP_OVL1_RDMA1		MTK_M4U_ID(SMI_L1_ID, 3)
#define M4U_PORT_L1_DISP_OVL1_HDR		MTK_M4U_ID(SMI_L1_ID, 4)
#define M4U_PORT_L1_DISP_WROT0			MTK_M4U_ID(SMI_L1_ID, 5)
#define M4U_PORT_L1_DISP_FAKE_ENG1		MTK_M4U_ID(SMI_L1_ID, 6)

/* LARB 2 -- VDO-1 */
#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(SMI_L2_ID, 0)
#define M4U_PORT_L2_MDP_RDMA2			MTK_M4U_ID(SMI_L2_ID, 1)
#define M4U_PORT_L2_MDP_RDMA4			MTK_M4U_ID(SMI_L2_ID, 2)
#define M4U_PORT_L2_MDP_RDMA6			MTK_M4U_ID(SMI_L2_ID, 3)
#define M4U_PORT_L2_DISP_FAKE1			MTK_M4U_ID(SMI_L2_ID, 4)

/* LARB 3 -- VDO-1 */
#define M4U_PORT_L3_MDP_RDMA1			MTK_M4U_ID(SMI_L3_ID, 0)

Annotation

Implementation Notes