include/dt-bindings/memory/mt8186-memory-port.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/memory/mt8186-memory-port.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/memory/mt8186-memory-port.h
Extension
.h
Size
9823 bytes
Lines
218
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_

#include <dt-bindings/memory/mtk-memory-port.h>

/*
 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
 * locate in anyone region. BUT:
 * a) Make sure all the ports inside a larb are in one range.
 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
 *
 * This is the suggested mapping in this SoC:
 *
 * modules    dma-address-region	larbs-ports
 * disp         0 ~ 4G                  larb0/1/2
 * vcodec      4G ~ 8G                  larb4/7
 * cam/mdp     8G ~ 12G                 the other larbs.
 * N/A         12G ~ 16G
 * CCU0   0x24000_0000 ~ 0x243ff_ffff   larb13: port 9/10
 * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb14: port 4/5
 */

/* MM IOMMU ports */
/* LARB 0 -- MMSYS */
#define IOMMU_PORT_L0_DISP_POSTMASK0	MTK_M4U_ID(0, 0)
#define IOMMU_PORT_L0_REVERSED		MTK_M4U_ID(0, 1)
#define IOMMU_PORT_L0_OVL_RDMA0		MTK_M4U_ID(0, 2)
#define IOMMU_PORT_L0_DISP_FAKE0	MTK_M4U_ID(0, 3)

/* LARB 1 -- MMSYS */
#define IOMMU_PORT_L1_DISP_RDMA1	MTK_M4U_ID(1, 0)
#define IOMMU_PORT_L1_OVL_2L_RDMA0	MTK_M4U_ID(1, 1)
#define IOMMU_PORT_L1_DISP_RDMA0	MTK_M4U_ID(1, 2)
#define IOMMU_PORT_L1_DISP_WDMA0	MTK_M4U_ID(1, 3)
#define IOMMU_PORT_L1_DISP_FAKE1	MTK_M4U_ID(1, 4)

/* LARB 2 -- MMSYS */
#define IOMMU_PORT_L2_MDP_RDMA0		MTK_M4U_ID(2, 0)
#define IOMMU_PORT_L2_MDP_RDMA1		MTK_M4U_ID(2, 1)
#define IOMMU_PORT_L2_MDP_WROT0		MTK_M4U_ID(2, 2)
#define IOMMU_PORT_L2_MDP_WROT1		MTK_M4U_ID(2, 3)
#define IOMMU_PORT_L2_DISP_FAKE0	MTK_M4U_ID(2, 4)

/* LARB 4 -- VDEC */
#define IOMMU_PORT_L4_HW_VDEC_MC_EXT		MTK_M4U_ID(4, 0)
#define IOMMU_PORT_L4_HW_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
#define IOMMU_PORT_L4_HW_VDEC_PP_EXT		MTK_M4U_ID(4, 2)
#define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(4, 3)
#define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(4, 4)
#define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(4, 5)
#define IOMMU_PORT_L4_HW_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
#define IOMMU_PORT_L4_HW_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
#define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
#define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(4, 9)
#define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT	MTK_M4U_ID(4, 10)
#define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 11)
#define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT	MTK_M4U_ID(4, 12)
#define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT	MTK_M4U_ID(4, 13)

/* LARB 7 -- VENC */
#define IOMMU_PORT_L7_VENC_RCPU		MTK_M4U_ID(7, 0)
#define IOMMU_PORT_L7_VENC_REC		MTK_M4U_ID(7, 1)
#define IOMMU_PORT_L7_VENC_BSDMA	MTK_M4U_ID(7, 2)
#define IOMMU_PORT_L7_VENC_SV_COMV	MTK_M4U_ID(7, 3)
#define IOMMU_PORT_L7_VENC_RD_COMV	MTK_M4U_ID(7, 4)
#define IOMMU_PORT_L7_VENC_CUR_LUMA	MTK_M4U_ID(7, 5)
#define IOMMU_PORT_L7_VENC_CUR_CHROMA	MTK_M4U_ID(7, 6)
#define IOMMU_PORT_L7_VENC_REF_LUMA	MTK_M4U_ID(7, 7)
#define IOMMU_PORT_L7_VENC_REF_CHROMA	MTK_M4U_ID(7, 8)
#define IOMMU_PORT_L7_JPGENC_Y_RDMA	MTK_M4U_ID(7, 9)
#define IOMMU_PORT_L7_JPGENC_C_RDMA	MTK_M4U_ID(7, 10)
#define IOMMU_PORT_L7_JPGENC_Q_TABLE	MTK_M4U_ID(7, 11)
#define IOMMU_PORT_L7_JPGENC_BSDMA	MTK_M4U_ID(7, 12)

/* LARB 8 -- WPE */
#define IOMMU_PORT_L8_WPE_RDMA_0	MTK_M4U_ID(8, 0)
#define IOMMU_PORT_L8_WPE_RDMA_1	MTK_M4U_ID(8, 1)
#define IOMMU_PORT_L8_WPE_WDMA_0	MTK_M4U_ID(8, 2)

/* LARB 9 -- IMG-1 */
#define IOMMU_PORT_L9_IMG_IMGI_D1	MTK_M4U_ID(9, 0)
#define IOMMU_PORT_L9_IMG_IMGBI_D1	MTK_M4U_ID(9, 1)
#define IOMMU_PORT_L9_IMG_DMGI_D1	MTK_M4U_ID(9, 2)
#define IOMMU_PORT_L9_IMG_DEPI_D1	MTK_M4U_ID(9, 3)
#define IOMMU_PORT_L9_IMG_LCE_D1	MTK_M4U_ID(9, 4)
#define IOMMU_PORT_L9_IMG_SMTI_D1	MTK_M4U_ID(9, 5)
#define IOMMU_PORT_L9_IMG_SMTO_D2	MTK_M4U_ID(9, 6)
#define IOMMU_PORT_L9_IMG_SMTO_D1	MTK_M4U_ID(9, 7)
#define IOMMU_PORT_L9_IMG_CRZO_D1	MTK_M4U_ID(9, 8)

Annotation

Implementation Notes