include/dt-bindings/memory/mt8192-larb-port.h

File Facts

System

Linux kernel

Corpus path

include/dt-bindings/memory/mt8192-larb-port.h

Extension

.h

Size

10301 bytes

Lines

244

Domain

Repository Root And Misc

Bucket

include

Inferred role

Repository Root And Misc: implementation source

Status

source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

• Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

• dt-bindings/memory/mtk-memory-port.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_

#include <dt-bindings/memory/mtk-memory-port.h>

/*
 * MM IOMMU supports 16GB dma address.
 *
 * The address will preassign like this:
 *
 * modules    dma-address-region	larbs-ports
 * disp         0 ~ 4G                   larb0/1
 * vcodec      4G ~ 8G                  larb4/5/7
 * cam/mdp     8G ~ 12G             larb2/9/11/13/14/16/17/18/19/20
 * CCU0    0x4000_0000 ~ 0x43ff_ffff     larb13: port 9/10
 * CCU1    0x4400_0000 ~ 0x47ff_ffff     larb14: port 4/5
 *
 * larb3/6/8/10/12/15 is null.
 */

/* larb0 */
#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(0, 0)
#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 1)
#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_ID(0, 2)
#define M4U_PORT_L0_DISP_RDMA0			MTK_M4U_ID(0, 3)
#define M4U_PORT_L0_DISP_WDMA0			MTK_M4U_ID(0, 4)
#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 5)

/* larb1 */
#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_ID(1, 0)
#define M4U_PORT_L1_OVL_2L_RDMA2_HDR		MTK_M4U_ID(1, 1)
#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 2)
#define M4U_PORT_L1_OVL_2L_RDMA2		MTK_M4U_ID(1, 3)
#define M4U_PORT_L1_DISP_MDP_RDMA4		MTK_M4U_ID(1, 4)
#define M4U_PORT_L1_DISP_RDMA4			MTK_M4U_ID(1, 5)
#define M4U_PORT_L1_DISP_UFBC_WDMA0		MTK_M4U_ID(1, 6)
#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_ID(1, 7)

/* larb2 */
#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
#define M4U_PORT_L2_MDP_RDMA1			MTK_M4U_ID(2, 1)
#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_ID(2, 2)
#define M4U_PORT_L2_MDP_WROT1			MTK_M4U_ID(2, 3)
#define M4U_PORT_L2_MDP_DISP_FAKE0		MTK_M4U_ID(2, 4)

/* larb3: null */

/* larb4 */
#define M4U_PORT_L4_VDEC_MC_EXT			MTK_M4U_ID(4, 0)
#define M4U_PORT_L4_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
#define M4U_PORT_L4_VDEC_PP_EXT			MTK_M4U_ID(4, 2)
#define M4U_PORT_L4_VDEC_PRED_RD_EXT		MTK_M4U_ID(4, 3)
#define M4U_PORT_L4_VDEC_PRED_WR_EXT		MTK_M4U_ID(4, 4)
#define M4U_PORT_L4_VDEC_PPWRAP_EXT		MTK_M4U_ID(4, 5)
#define M4U_PORT_L4_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
#define M4U_PORT_L4_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
#define M4U_PORT_L4_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
#define M4U_PORT_L4_VDEC_AVC_MV_EXT		MTK_M4U_ID(4, 9)
#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 10)

/* larb5 */
#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT		MTK_M4U_ID(5, 0)
#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT		MTK_M4U_ID(5, 1)
#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT	MTK_M4U_ID(5, 2)
#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT	MTK_M4U_ID(5, 3)
#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT		MTK_M4U_ID(5, 4)
#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT		MTK_M4U_ID(5, 5)
#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT	MTK_M4U_ID(5, 6)
#define M4U_PORT_L5_VDEC_UFO_ENC_EXT		MTK_M4U_ID(5, 7)

/* larb6: null */

/* larb7 */
#define M4U_PORT_L7_VENC_RCPU			MTK_M4U_ID(7, 0)
#define M4U_PORT_L7_VENC_REC			MTK_M4U_ID(7, 1)
#define M4U_PORT_L7_VENC_BSDMA			MTK_M4U_ID(7, 2)
#define M4U_PORT_L7_VENC_SV_COMV		MTK_M4U_ID(7, 3)
#define M4U_PORT_L7_VENC_RD_COMV		MTK_M4U_ID(7, 4)
#define M4U_PORT_L7_VENC_CUR_LUMA		MTK_M4U_ID(7, 5)
#define M4U_PORT_L7_VENC_CUR_CHROMA		MTK_M4U_ID(7, 6)
#define M4U_PORT_L7_VENC_REF_LUMA		MTK_M4U_ID(7, 7)
#define M4U_PORT_L7_VENC_REF_CHROMA		MTK_M4U_ID(7, 8)
#define M4U_PORT_L7_JPGENC_Y_RDMA		MTK_M4U_ID(7, 9)
#define M4U_PORT_L7_JPGENC_Q_RDMA		MTK_M4U_ID(7, 10)
#define M4U_PORT_L7_JPGENC_C_TABLE		MTK_M4U_ID(7, 11)
#define M4U_PORT_L7_JPGENC_BSDMA		MTK_M4U_ID(7, 12)
#define M4U_PORT_L7_VENC_SUB_R_LUMA		MTK_M4U_ID(7, 13)
#define M4U_PORT_L7_VENC_SUB_W_LUMA		MTK_M4U_ID(7, 14)

/* larb8: null */

Annotation

• Immediate include surface: `dt-bindings/memory/mtk-memory-port.h`.
• Atlas domain: Repository Root And Misc / include.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.