include/dt-bindings/memory/mt8195-memory-port.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/memory/mt8195-memory-port.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/memory/mt8195-memory-port.h
Extension
.h
Size
18766 bytes
Lines
409
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_

#include <dt-bindings/memory/mtk-memory-port.h>

/*
 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
 * locate in anyone region. BUT:
 * a) Make sure all the ports inside a larb are in one range.
 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
 *
 * This is the suggested mapping in this SoC:
 *
 * modules    dma-address-region	larbs-ports
 * disp         0 ~ 4G                  larb0/1/2/3
 * vcodec      4G ~ 8G                  larb19/20/21/22/23/24
 * cam/mdp     8G ~ 12G                 the other larbs.
 * N/A         12G ~ 16G
 * CCU0   0x24000_0000 ~ 0x243ff_ffff   larb18: port 0/1
 * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb18: port 2/3
 *
 * This SoC have two IOMMU HWs, this is the detailed connected information:
 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
 */

/* MM IOMMU ports */
/* larb0 */
#define M4U_PORT_L0_DISP_RDMA0			MTK_M4U_ID(0, 0)
#define M4U_PORT_L0_DISP_WDMA0			MTK_M4U_ID(0, 1)
#define M4U_PORT_L0_DISP_OVL0_RDMA0		MTK_M4U_ID(0, 2)
#define M4U_PORT_L0_DISP_OVL0_RDMA1		MTK_M4U_ID(0, 3)
#define M4U_PORT_L0_DISP_OVL0_HDR		MTK_M4U_ID(0, 4)
#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 5)

/* larb1 */
#define M4U_PORT_L1_DISP_RDMA0			MTK_M4U_ID(1, 0)
#define M4U_PORT_L1_DISP_WDMA0			MTK_M4U_ID(1, 1)
#define M4U_PORT_L1_DISP_OVL0_RDMA0		MTK_M4U_ID(1, 2)
#define M4U_PORT_L1_DISP_OVL0_RDMA1		MTK_M4U_ID(1, 3)
#define M4U_PORT_L1_DISP_OVL0_HDR		MTK_M4U_ID(1, 4)
#define M4U_PORT_L1_DISP_FAKE0			MTK_M4U_ID(1, 5)

/* larb2 */
#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
#define M4U_PORT_L2_MDP_RDMA2			MTK_M4U_ID(2, 1)
#define M4U_PORT_L2_MDP_RDMA4			MTK_M4U_ID(2, 2)
#define M4U_PORT_L2_MDP_RDMA6			MTK_M4U_ID(2, 3)
#define M4U_PORT_L2_DISP_FAKE1			MTK_M4U_ID(2, 4)

/* larb3 */
#define M4U_PORT_L3_MDP_RDMA1			MTK_M4U_ID(3, 0)
#define M4U_PORT_L3_MDP_RDMA3			MTK_M4U_ID(3, 1)
#define M4U_PORT_L3_MDP_RDMA5			MTK_M4U_ID(3, 2)
#define M4U_PORT_L3_MDP_RDMA7			MTK_M4U_ID(3, 3)
#define M4U_PORT_L3_HDR_DS			MTK_M4U_ID(3, 4)
#define M4U_PORT_L3_HDR_ADL			MTK_M4U_ID(3, 5)
#define M4U_PORT_L3_DISP_FAKE1			MTK_M4U_ID(3, 6)

/* larb4 */
#define M4U_PORT_L4_MDP_RDMA			MTK_M4U_ID(4, 0)
#define M4U_PORT_L4_MDP_FG			MTK_M4U_ID(4, 1)
#define M4U_PORT_L4_MDP_OVL			MTK_M4U_ID(4, 2)
#define M4U_PORT_L4_MDP_WROT			MTK_M4U_ID(4, 3)
#define M4U_PORT_L4_FAKE			MTK_M4U_ID(4, 4)

/* larb5 */
#define M4U_PORT_L5_SVPP1_MDP_RDMA		MTK_M4U_ID(5, 0)
#define M4U_PORT_L5_SVPP1_MDP_FG		MTK_M4U_ID(5, 1)
#define M4U_PORT_L5_SVPP1_MDP_OVL		MTK_M4U_ID(5, 2)
#define M4U_PORT_L5_SVPP1_MDP_WROT		MTK_M4U_ID(5, 3)
#define M4U_PORT_L5_SVPP2_MDP_RDMA		MTK_M4U_ID(5, 4)
#define M4U_PORT_L5_SVPP2_MDP_FG		MTK_M4U_ID(5, 5)
#define M4U_PORT_L5_SVPP2_MDP_WROT		MTK_M4U_ID(5, 6)
#define M4U_PORT_L5_FAKE			MTK_M4U_ID(5, 7)

/* larb6 */
#define M4U_PORT_L6_SVPP3_MDP_RDMA		MTK_M4U_ID(6, 0)
#define M4U_PORT_L6_SVPP3_MDP_FG		MTK_M4U_ID(6, 1)
#define M4U_PORT_L6_SVPP3_MDP_WROT		MTK_M4U_ID(6, 2)
#define M4U_PORT_L6_FAKE			MTK_M4U_ID(6, 3)

/* larb7 */
#define M4U_PORT_L7_IMG_WPE_RDMA0		MTK_M4U_ID(7, 0)
#define M4U_PORT_L7_IMG_WPE_RDMA1		MTK_M4U_ID(7, 1)
#define M4U_PORT_L7_IMG_WPE_WDMA0		MTK_M4U_ID(7, 2)

/* larb8 */
#define M4U_PORT_L8_IMG_WPE_RDMA0		MTK_M4U_ID(8, 0)

Annotation

Implementation Notes