include/dt-bindings/memory/nvidia,tegra264.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/memory/nvidia,tegra264.h

File Facts

System: Linux kernel
Corpus path: include/dt-bindings/memory/nvidia,tegra264.h
Extension: .h
Size: 16641 bytes
Lines: 424
Domain: Repository Root And Misc
Bucket: include
Inferred role: Repository Root And Misc: implementation source
Status: source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
#define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H

#define TEGRA264_SID(x) ((x) << 8)

/*
 * SMMU stream IDs
 */

#define TEGRA264_SID_AON       TEGRA264_SID(0x01)
#define TEGRA264_SID_APE       TEGRA264_SID(0x02)
#define TEGRA264_SID_ETR       TEGRA264_SID(0x03)
#define TEGRA264_SID_BPMP      TEGRA264_SID(0x04)
#define TEGRA264_SID_DCE       TEGRA264_SID(0x05)
#define TEGRA264_SID_EQOS      TEGRA264_SID(0x06)
#define TEGRA264_SID_GPCDMA    TEGRA264_SID(0x08)
#define TEGRA264_SID_DISP      TEGRA264_SID(0x09)
#define TEGRA264_SID_HDA       TEGRA264_SID(0x0a)
#define TEGRA264_SID_HOST1X    TEGRA264_SID(0x0b)
#define TEGRA264_SID_ISP0      TEGRA264_SID(0x0c)
#define TEGRA264_SID_ISP1      TEGRA264_SID(0x0d)
#define TEGRA264_SID_PMA0      TEGRA264_SID(0x0e)
#define TEGRA264_SID_FSI0      TEGRA264_SID(0x0f)
#define TEGRA264_SID_FSI1      TEGRA264_SID(0x10)
#define TEGRA264_SID_PVA       TEGRA264_SID(0x11)
#define TEGRA264_SID_SDMMC0    TEGRA264_SID(0x12)
#define TEGRA264_SID_MGBE0     TEGRA264_SID(0x13)
#define TEGRA264_SID_MGBE1     TEGRA264_SID(0x14)
#define TEGRA264_SID_MGBE2     TEGRA264_SID(0x15)
#define TEGRA264_SID_MGBE3     TEGRA264_SID(0x16)
#define TEGRA264_SID_MSSSEQ    TEGRA264_SID(0x17)
#define TEGRA264_SID_SE        TEGRA264_SID(0x18)
#define TEGRA264_SID_SEU1      TEGRA264_SID(0x19)
#define TEGRA264_SID_SEU2      TEGRA264_SID(0x1a)
#define TEGRA264_SID_SEU3      TEGRA264_SID(0x1b)
#define TEGRA264_SID_PSC       TEGRA264_SID(0x1c)
#define TEGRA264_SID_OESP      TEGRA264_SID(0x23)
#define TEGRA264_SID_SB        TEGRA264_SID(0x24)
#define TEGRA264_SID_XSPI0     TEGRA264_SID(0x25)
#define TEGRA264_SID_TSEC      TEGRA264_SID(0x29)
#define TEGRA264_SID_UFS       TEGRA264_SID(0x2a)
#define TEGRA264_SID_RCE       TEGRA264_SID(0x2b)
#define TEGRA264_SID_RCE1      TEGRA264_SID(0x2c)
#define TEGRA264_SID_VI        TEGRA264_SID(0x2e)
#define TEGRA264_SID_VI1       TEGRA264_SID(0x2f)
#define TEGRA264_SID_VIC       TEGRA264_SID(0x30)
#define TEGRA264_SID_XUSB_DEV  TEGRA264_SID(0x32)
#define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33)
#define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34)
#define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35)
#define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36)
#define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37)

/*
 * memory client IDs
 */

/* PTW read client mapped to SOC SMMU0 */
#define TEGRA264_MEMORY_CLIENT_PTCR		0x00
/* HOST1X read client */
#define TEGRA264_MEMORY_CLIENT_HOST1XR		0x16
#define TEGRA264_MEMORY_CLIENT_MPCORER		0x27
/* Platform security (PSC) Read clients */
#define TEGRA264_MEMORY_CLIENT_PSCR		0x33
/* PSC Write clients */
#define TEGRA264_MEMORY_CLIENT_PSCW		0x34
/* ISP0 Read client */
#define TEGRA264_MEMORY_CLIENT_ISP0R		0x37
#define TEGRA264_MEMORY_CLIENT_MPCOREW		0x39
/* ISP0 Write client */
#define TEGRA264_MEMORY_CLIENT_ISP0W		0x44
/* ISP1 Write client */
#define TEGRA264_MEMORY_CLIENT_ISP1W		0x45
/* ISP FALCON Read client */
#define TEGRA264_MEMORY_CLIENT_ISPFALCONR	0x47
/* ISP FALCON Write client */
#define TEGRA264_MEMORY_CLIENT_ISPFALCONW	0x4f
/* MGBE2 Read mccif */
#define TEGRA264_MEMORY_CLIENT_MGBE2R		0x5c
#define TEGRA264_MEMORY_CLIENT_OFAR2MC		0x5d
#define TEGRA264_MEMORY_CLIENT_OFAW2MC		0x5e
/* MGBE2 Write mccif */
#define TEGRA264_MEMORY_CLIENT_MGBE2W		0x5f
/* MGBE3 Read mccif */
#define TEGRA264_MEMORY_CLIENT_MGBE3R		0x61
/* MGBE3 Write mccif */
#define TEGRA264_MEMORY_CLIENT_MGBE3W		0x65
/* SEU1 Memory Read Client */
#define TEGRA264_MEMORY_CLIENT_SEU1RD		0x68
/* SEU1 Memory Write Client */

Annotation

Atlas domain: Repository Root And Misc / include.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.