include/dt-bindings/pinctrl/k210-fpioa.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/pinctrl/k210-fpioa.h

File Facts

System: Linux kernel
Corpus path: include/dt-bindings/pinctrl/k210-fpioa.h
Extension: .h
Size: 15067 bytes
Lines: 277
Domain: Repository Root And Misc
Bucket: include
Inferred role: Repository Root And Misc: implementation source
Status: source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef PINCTRL_K210_FPIOA_H
#define PINCTRL_K210_FPIOA_H

/*
 * Full list of FPIOA functions from
 * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
 */
#define K210_PCF_MASK		GENMASK(7, 0)
#define K210_PCF_JTAG_TCLK	0   /* JTAG Test Clock */
#define K210_PCF_JTAG_TDI	1   /* JTAG Test Data In */
#define K210_PCF_JTAG_TMS	2   /* JTAG Test Mode Select */
#define K210_PCF_JTAG_TDO	3   /* JTAG Test Data Out */
#define K210_PCF_SPI0_D0	4   /* SPI0 Data 0 */
#define K210_PCF_SPI0_D1	5   /* SPI0 Data 1 */
#define K210_PCF_SPI0_D2	6   /* SPI0 Data 2 */
#define K210_PCF_SPI0_D3	7   /* SPI0 Data 3 */
#define K210_PCF_SPI0_D4	8   /* SPI0 Data 4 */
#define K210_PCF_SPI0_D5	9   /* SPI0 Data 5 */
#define K210_PCF_SPI0_D6	10  /* SPI0 Data 6 */
#define K210_PCF_SPI0_D7	11  /* SPI0 Data 7 */
#define K210_PCF_SPI0_SS0	12  /* SPI0 Chip Select 0 */
#define K210_PCF_SPI0_SS1	13  /* SPI0 Chip Select 1 */
#define K210_PCF_SPI0_SS2	14  /* SPI0 Chip Select 2 */
#define K210_PCF_SPI0_SS3	15  /* SPI0 Chip Select 3 */
#define K210_PCF_SPI0_ARB	16  /* SPI0 Arbitration */
#define K210_PCF_SPI0_SCLK	17  /* SPI0 Serial Clock */
#define K210_PCF_UARTHS_RX	18  /* UART High speed Receiver */
#define K210_PCF_UARTHS_TX	19  /* UART High speed Transmitter */
#define K210_PCF_RESV6		20  /* Reserved function */
#define K210_PCF_RESV7		21  /* Reserved function */
#define K210_PCF_CLK_SPI1	22  /* Clock SPI1 */
#define K210_PCF_CLK_I2C1	23  /* Clock I2C1 */
#define K210_PCF_GPIOHS0	24  /* GPIO High speed 0 */
#define K210_PCF_GPIOHS1	25  /* GPIO High speed 1 */
#define K210_PCF_GPIOHS2	26  /* GPIO High speed 2 */
#define K210_PCF_GPIOHS3	27  /* GPIO High speed 3 */
#define K210_PCF_GPIOHS4	28  /* GPIO High speed 4 */
#define K210_PCF_GPIOHS5	29  /* GPIO High speed 5 */
#define K210_PCF_GPIOHS6	30  /* GPIO High speed 6 */
#define K210_PCF_GPIOHS7	31  /* GPIO High speed 7 */
#define K210_PCF_GPIOHS8	32  /* GPIO High speed 8 */
#define K210_PCF_GPIOHS9	33  /* GPIO High speed 9 */
#define K210_PCF_GPIOHS10	34  /* GPIO High speed 10 */
#define K210_PCF_GPIOHS11	35  /* GPIO High speed 11 */
#define K210_PCF_GPIOHS12	36  /* GPIO High speed 12 */
#define K210_PCF_GPIOHS13	37  /* GPIO High speed 13 */
#define K210_PCF_GPIOHS14	38  /* GPIO High speed 14 */
#define K210_PCF_GPIOHS15	39  /* GPIO High speed 15 */
#define K210_PCF_GPIOHS16	40  /* GPIO High speed 16 */
#define K210_PCF_GPIOHS17	41  /* GPIO High speed 17 */
#define K210_PCF_GPIOHS18	42  /* GPIO High speed 18 */
#define K210_PCF_GPIOHS19	43  /* GPIO High speed 19 */
#define K210_PCF_GPIOHS20	44  /* GPIO High speed 20 */
#define K210_PCF_GPIOHS21	45  /* GPIO High speed 21 */
#define K210_PCF_GPIOHS22	46  /* GPIO High speed 22 */
#define K210_PCF_GPIOHS23	47  /* GPIO High speed 23 */
#define K210_PCF_GPIOHS24	48  /* GPIO High speed 24 */
#define K210_PCF_GPIOHS25	49  /* GPIO High speed 25 */
#define K210_PCF_GPIOHS26	50  /* GPIO High speed 26 */
#define K210_PCF_GPIOHS27	51  /* GPIO High speed 27 */
#define K210_PCF_GPIOHS28	52  /* GPIO High speed 28 */
#define K210_PCF_GPIOHS29	53  /* GPIO High speed 29 */
#define K210_PCF_GPIOHS30	54  /* GPIO High speed 30 */
#define K210_PCF_GPIOHS31	55  /* GPIO High speed 31 */
#define K210_PCF_GPIO0		56  /* GPIO pin 0 */
#define K210_PCF_GPIO1		57  /* GPIO pin 1 */
#define K210_PCF_GPIO2		58  /* GPIO pin 2 */
#define K210_PCF_GPIO3		59  /* GPIO pin 3 */
#define K210_PCF_GPIO4		60  /* GPIO pin 4 */
#define K210_PCF_GPIO5		61  /* GPIO pin 5 */
#define K210_PCF_GPIO6		62  /* GPIO pin 6 */
#define K210_PCF_GPIO7		63  /* GPIO pin 7 */
#define K210_PCF_UART1_RX	64  /* UART1 Receiver */
#define K210_PCF_UART1_TX	65  /* UART1 Transmitter */
#define K210_PCF_UART2_RX	66  /* UART2 Receiver */
#define K210_PCF_UART2_TX	67  /* UART2 Transmitter */
#define K210_PCF_UART3_RX	68  /* UART3 Receiver */
#define K210_PCF_UART3_TX	69  /* UART3 Transmitter */
#define K210_PCF_SPI1_D0	70  /* SPI1 Data 0 */
#define K210_PCF_SPI1_D1	71  /* SPI1 Data 1 */
#define K210_PCF_SPI1_D2	72  /* SPI1 Data 2 */
#define K210_PCF_SPI1_D3	73  /* SPI1 Data 3 */
#define K210_PCF_SPI1_D4	74  /* SPI1 Data 4 */
#define K210_PCF_SPI1_D5	75  /* SPI1 Data 5 */
#define K210_PCF_SPI1_D6	76  /* SPI1 Data 6 */
#define K210_PCF_SPI1_D7	77  /* SPI1 Data 7 */
#define K210_PCF_SPI1_SS0	78  /* SPI1 Chip Select 0 */
#define K210_PCF_SPI1_SS1	79  /* SPI1 Chip Select 1 */
#define K210_PCF_SPI1_SS2	80  /* SPI1 Chip Select 2 */
#define K210_PCF_SPI1_SS3	81  /* SPI1 Chip Select 3 */

Annotation

Atlas domain: Repository Root And Misc / include.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.