include/dt-bindings/pinctrl/pinctrl-sg2042.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/pinctrl/pinctrl-sg2042.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/pinctrl/pinctrl-sg2042.h- Extension
.h- Size
- 5272 bytes
- Lines
- 197
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_PINCTRL_SG2042_H
#define _DT_BINDINGS_PINCTRL_SG2042_H
#define PINMUX(pin, mux) \
(((pin) & 0xffff) | (((mux) & 0xff) << 16))
#define PIN_LPC_LCLK 0
#define PIN_LPC_LFRAME 1
#define PIN_LPC_LAD0 2
#define PIN_LPC_LAD1 3
#define PIN_LPC_LAD2 4
#define PIN_LPC_LAD3 5
#define PIN_LPC_LDRQ0 6
#define PIN_LPC_LDRQ1 7
#define PIN_LPC_SERIRQ 8
#define PIN_LPC_CLKRUN 9
#define PIN_LPC_LPME 10
#define PIN_LPC_LPCPD 11
#define PIN_LPC_LSMI 12
#define PIN_PCIE0_L0_RESET 13
#define PIN_PCIE0_L1_RESET 14
#define PIN_PCIE0_L0_WAKEUP 15
#define PIN_PCIE0_L1_WAKEUP 16
#define PIN_PCIE0_L0_CLKREQ_IN 17
#define PIN_PCIE0_L1_CLKREQ_IN 18
#define PIN_PCIE1_L0_RESET 19
#define PIN_PCIE1_L1_RESET 20
#define PIN_PCIE1_L0_WAKEUP 21
#define PIN_PCIE1_L1_WAKEUP 22
#define PIN_PCIE1_L0_CLKREQ_IN 23
#define PIN_PCIE1_L1_CLKREQ_IN 24
#define PIN_SPIF0_CLK_SEL1 25
#define PIN_SPIF0_CLK_SEL0 26
#define PIN_SPIF0_WP 27
#define PIN_SPIF0_HOLD 28
#define PIN_SPIF0_SDI 29
#define PIN_SPIF0_CS 30
#define PIN_SPIF0_SCK 31
#define PIN_SPIF0_SDO 32
#define PIN_SPIF1_CLK_SEL1 33
#define PIN_SPIF1_CLK_SEL0 34
#define PIN_SPIF1_WP 35
#define PIN_SPIF1_HOLD 36
#define PIN_SPIF1_SDI 37
#define PIN_SPIF1_CS 38
#define PIN_SPIF1_SCK 39
#define PIN_SPIF1_SDO 40
#define PIN_EMMC_WP 41
#define PIN_EMMC_CD 42
#define PIN_EMMC_RST 43
#define PIN_EMMC_PWR_EN 44
#define PIN_SDIO_CD 45
#define PIN_SDIO_WP 46
#define PIN_SDIO_RST 47
#define PIN_SDIO_PWR_EN 48
#define PIN_RGMII0_TXD0 49
#define PIN_RGMII0_TXD1 50
#define PIN_RGMII0_TXD2 51
#define PIN_RGMII0_TXD3 52
#define PIN_RGMII0_TXCTRL 53
#define PIN_RGMII0_RXD0 54
#define PIN_RGMII0_RXD1 55
#define PIN_RGMII0_RXD2 56
#define PIN_RGMII0_RXD3 57
#define PIN_RGMII0_RXCTRL 58
#define PIN_RGMII0_TXC 59
#define PIN_RGMII0_RXC 60
#define PIN_RGMII0_REFCLKO 61
#define PIN_RGMII0_IRQ 62
#define PIN_RGMII0_MDC 63
#define PIN_RGMII0_MDIO 64
#define PIN_PWM0 65
#define PIN_PWM1 66
#define PIN_PWM2 67
#define PIN_PWM3 68
#define PIN_FAN0 69
#define PIN_FAN1 70
#define PIN_FAN2 71
#define PIN_FAN3 72
#define PIN_IIC0_SDA 73
#define PIN_IIC0_SCL 74
#define PIN_IIC1_SDA 75
#define PIN_IIC1_SCL 76
#define PIN_IIC2_SDA 77
#define PIN_IIC2_SCL 78
#define PIN_IIC3_SDA 79
#define PIN_IIC3_SCL 80
#define PIN_UART0_TX 81
#define PIN_UART0_RX 82
#define PIN_UART0_RTS 83
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.