include/dt-bindings/pinctrl/pinctrl-sg2044.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/pinctrl/pinctrl-sg2044.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/pinctrl/pinctrl-sg2044.h- Extension
.h- Size
- 6140 bytes
- Lines
- 222
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_PINCTRL_SG2044_H
#define _DT_BINDINGS_PINCTRL_SG2044_H
#define PINMUX(pin, mux) \
(((pin) & 0xffff) | (((mux) & 0xff) << 16))
#define PIN_IIC0_SMBSUS_IN 0
#define PIN_IIC0_SMBSUS_OUT 1
#define PIN_IIC0_SMBALERT 2
#define PIN_IIC1_SMBSUS_IN 3
#define PIN_IIC1_SMBSUS_OUT 4
#define PIN_IIC1_SMBALERT 5
#define PIN_IIC2_SMBSUS_IN 6
#define PIN_IIC2_SMBSUS_OUT 7
#define PIN_IIC2_SMBALERT 8
#define PIN_IIC3_SMBSUS_IN 9
#define PIN_IIC3_SMBSUS_OUT 10
#define PIN_IIC3_SMBALERT 11
#define PIN_PCIE0_L0_RESET 12
#define PIN_PCIE0_L1_RESET 13
#define PIN_PCIE0_L0_WAKEUP 14
#define PIN_PCIE0_L1_WAKEUP 15
#define PIN_PCIE0_L0_CLKREQ_IN 16
#define PIN_PCIE0_L1_CLKREQ_IN 17
#define PIN_PCIE1_L0_RESET 18
#define PIN_PCIE1_L1_RESET 19
#define PIN_PCIE1_L0_WAKEUP 20
#define PIN_PCIE1_L1_WAKEUP 21
#define PIN_PCIE1_L0_CLKREQ_IN 22
#define PIN_PCIE1_L1_CLKREQ_IN 23
#define PIN_PCIE2_L0_RESET 24
#define PIN_PCIE2_L1_RESET 25
#define PIN_PCIE2_L0_WAKEUP 26
#define PIN_PCIE2_L1_WAKEUP 27
#define PIN_PCIE2_L0_CLKREQ_IN 28
#define PIN_PCIE2_L1_CLKREQ_IN 29
#define PIN_PCIE3_L0_RESET 30
#define PIN_PCIE3_L1_RESET 31
#define PIN_PCIE3_L0_WAKEUP 32
#define PIN_PCIE3_L1_WAKEUP 33
#define PIN_PCIE3_L0_CLKREQ_IN 34
#define PIN_PCIE3_L1_CLKREQ_IN 35
#define PIN_PCIE4_L0_RESET 36
#define PIN_PCIE4_L1_RESET 37
#define PIN_PCIE4_L0_WAKEUP 38
#define PIN_PCIE4_L1_WAKEUP 39
#define PIN_PCIE4_L0_CLKREQ_IN 40
#define PIN_PCIE4_L1_CLKREQ_IN 41
#define PIN_SPIF0_CLK_SEL1 42
#define PIN_SPIF0_CLK_SEL0 43
#define PIN_SPIF0_WP 44
#define PIN_SPIF0_HOLD 45
#define PIN_SPIF0_SDI 46
#define PIN_SPIF0_CS 47
#define PIN_SPIF0_SCK 48
#define PIN_SPIF0_SDO 49
#define PIN_SPIF1_CLK_SEL1 50
#define PIN_SPIF1_CLK_SEL0 51
#define PIN_SPIF1_WP 52
#define PIN_SPIF1_HOLD 53
#define PIN_SPIF1_SDI 54
#define PIN_SPIF1_CS 55
#define PIN_SPIF1_SCK 56
#define PIN_SPIF1_SDO 57
#define PIN_EMMC_WP 58
#define PIN_EMMC_CD 59
#define PIN_EMMC_RST 60
#define PIN_EMMC_PWR_EN 61
#define PIN_SDIO_CD 62
#define PIN_SDIO_WP 63
#define PIN_SDIO_RST 64
#define PIN_SDIO_PWR_EN 65
#define PIN_RGMII0_TXD0 66
#define PIN_RGMII0_TXD1 67
#define PIN_RGMII0_TXD2 68
#define PIN_RGMII0_TXD3 69
#define PIN_RGMII0_TXCTRL 70
#define PIN_RGMII0_RXD0 71
#define PIN_RGMII0_RXD1 72
#define PIN_RGMII0_RXD2 73
#define PIN_RGMII0_RXD3 74
#define PIN_RGMII0_RXCTRL 75
#define PIN_RGMII0_TXC 76
#define PIN_RGMII0_RXC 77
#define PIN_RGMII0_REFCLKO 78
#define PIN_RGMII0_IRQ 79
#define PIN_RGMII0_MDC 80
#define PIN_RGMII0_MDIO 81
#define PIN_PWM0 82
#define PIN_PWM1 83
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.