include/dt-bindings/reset/qcom,ipq5210-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/reset/qcom,ipq5210-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/reset/qcom,ipq5210-gcc.h
Extension
.h
Size
4429 bytes
Lines
128
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H
#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H

#define GCC_ADSS_BCR						0
#define GCC_ADSS_PWM_ARES					1
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			2
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES		3
#define GCC_APSS_AHB_ARES					4
#define GCC_APSS_ATB_ARES					5
#define GCC_APSS_AXI_ARES					6
#define GCC_APSS_TS_ARES					7
#define GCC_BOOT_ROM_AHB_ARES					8
#define GCC_BOOT_ROM_BCR					9
#define GCC_GEPHY_BCR						10
#define GCC_GEPHY_SYS_ARES					11
#define GCC_GP1_ARES						12
#define GCC_GP2_ARES						13
#define GCC_GP3_ARES						14
#define GCC_MDIO_AHB_ARES					15
#define GCC_MDIO_BCR						16
#define GCC_MDIO_GEPHY_AHB_ARES					17
#define GCC_NSS_BCR						18
#define GCC_NSS_TS_ARES						19
#define GCC_NSSCC_ARES						20
#define GCC_NSSCFG_ARES						21
#define GCC_NSSNOC_ATB_ARES					22
#define GCC_NSSNOC_MEMNOC_1_ARES				23
#define GCC_NSSNOC_MEMNOC_ARES					24
#define GCC_NSSNOC_NSSCC_ARES					25
#define GCC_NSSNOC_PCNOC_1_ARES					26
#define GCC_NSSNOC_QOSGEN_REF_ARES				27
#define GCC_NSSNOC_SNOC_1_ARES					28
#define GCC_NSSNOC_SNOC_ARES					29
#define GCC_NSSNOC_TIMEOUT_REF_ARES				30
#define GCC_NSSNOC_XO_DCD_ARES					31
#define GCC_PCIE0_AHB_ARES					32
#define GCC_PCIE0_AUX_ARES					33
#define GCC_PCIE0_AXI_M_ARES					34
#define GCC_PCIE0_AXI_S_BRIDGE_ARES				35
#define GCC_PCIE0_AXI_S_ARES					36
#define GCC_PCIE0_BCR						37
#define GCC_PCIE0_LINK_DOWN_BCR					38
#define GCC_PCIE0_PHY_BCR					39
#define GCC_PCIE0_PIPE_ARES					40
#define GCC_PCIE0PHY_PHY_BCR					41
#define GCC_PCIE1_AHB_ARES					42
#define GCC_PCIE1_AUX_ARES					43
#define GCC_PCIE1_AXI_M_ARES					44
#define GCC_PCIE1_AXI_S_BRIDGE_ARES				45
#define GCC_PCIE1_AXI_S_ARES					46
#define GCC_PCIE1_BCR						47
#define GCC_PCIE1_LINK_DOWN_BCR					48
#define GCC_PCIE1_PHY_BCR					49
#define GCC_PCIE1_PIPE_ARES					50
#define GCC_PCIE1PHY_PHY_BCR					51
#define GCC_QRNG_AHB_ARES					52
#define GCC_QRNG_BCR						53
#define GCC_QUPV3_2X_CORE_ARES					54
#define GCC_QUPV3_AHB_MST_ARES					55
#define GCC_QUPV3_AHB_SLV_ARES					56
#define GCC_QUPV3_BCR						57
#define GCC_QUPV3_CORE_ARES					58
#define GCC_QUPV3_WRAP_SE0_ARES					59
#define GCC_QUPV3_WRAP_SE0_BCR					60
#define GCC_QUPV3_WRAP_SE1_ARES					61
#define GCC_QUPV3_WRAP_SE1_BCR					62
#define GCC_QUPV3_WRAP_SE2_ARES					63
#define GCC_QUPV3_WRAP_SE2_BCR					64
#define GCC_QUPV3_WRAP_SE3_ARES					65
#define GCC_QUPV3_WRAP_SE3_BCR					66
#define GCC_QUPV3_WRAP_SE4_ARES					67
#define GCC_QUPV3_WRAP_SE4_BCR					68
#define GCC_QUPV3_WRAP_SE5_ARES					69
#define GCC_QUPV3_WRAP_SE5_BCR					70
#define GCC_QUSB2_0_PHY_BCR					71
#define GCC_SDCC1_AHB_ARES					72
#define GCC_SDCC1_APPS_ARES					73
#define GCC_SDCC1_ICE_CORE_ARES					74
#define GCC_SDCC_BCR						75
#define GCC_TLMM_AHB_ARES					76
#define GCC_TLMM_ARES						77
#define GCC_TLMM_BCR						78
#define GCC_UNIPHY0_AHB_ARES					79
#define GCC_UNIPHY0_BCR						80
#define GCC_UNIPHY0_SYS_ARES					81
#define GCC_UNIPHY1_AHB_ARES					82
#define GCC_UNIPHY1_BCR						83
#define GCC_UNIPHY1_SYS_ARES					84
#define GCC_UNIPHY2_AHB_ARES					85
#define GCC_UNIPHY2_BCR						86

Annotation

Implementation Notes