include/dt-bindings/reset/qcom,ipq5424-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/reset/qcom,ipq5424-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/reset/qcom,ipq5424-gcc.h
Extension
.h
Size
10664 bytes
Lines
311
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H
#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H

#define GCC_QUPV3_BCR				0
#define GCC_QUPV3_I2C0_BCR			1
#define GCC_QUPV3_UART0_BCR			2
#define GCC_QUPV3_I2C1_BCR			3
#define GCC_QUPV3_UART1_BCR			4
#define GCC_QUPV3_SPI0_BCR			5
#define GCC_QUPV3_SPI1_BCR			6
#define GCC_IMEM_BCR				7
#define GCC_TME_BCR				8
#define GCC_DDRSS_BCR				9
#define GCC_PRNG_BCR				10
#define GCC_BOOT_ROM_BCR			11
#define GCC_NSS_BCR				12
#define GCC_MDIO_BCR				13
#define GCC_UNIPHY0_BCR				14
#define GCC_UNIPHY1_BCR				15
#define GCC_UNIPHY2_BCR				16
#define GCC_WCSS_BCR				17
#define GCC_SEC_CTRL_BCR			19
#define GCC_TME_SEC_BUS_BCR			20
#define GCC_ADSS_BCR				21
#define GCC_LPASS_BCR				22
#define GCC_PCIE0_BCR				23
#define GCC_PCIE0_LINK_DOWN_BCR			24
#define GCC_PCIE0PHY_PHY_BCR			25
#define GCC_PCIE0_PHY_BCR			26
#define GCC_PCIE1_BCR				27
#define GCC_PCIE1_LINK_DOWN_BCR			28
#define GCC_PCIE1PHY_PHY_BCR			29
#define GCC_PCIE1_PHY_BCR			30
#define GCC_PCIE2_BCR				31
#define GCC_PCIE2_LINK_DOWN_BCR			32
#define GCC_PCIE2PHY_PHY_BCR			33
#define GCC_PCIE2_PHY_BCR			34
#define GCC_PCIE3_BCR				35
#define GCC_PCIE3_LINK_DOWN_BCR			36
#define GCC_PCIE3PHY_PHY_BCR			37
#define GCC_PCIE3_PHY_BCR			38
#define GCC_USB_BCR				39
#define GCC_QUSB2_0_PHY_BCR			40
#define GCC_USB0_PHY_BCR			41
#define GCC_USB3PHY_0_PHY_BCR			42
#define GCC_QDSS_BCR				43
#define GCC_SNOC_BCR				44
#define GCC_ANOC_BCR				45
#define GCC_PCNOC_BCR				46
#define GCC_PCNOC_BUS_TIMEOUT0_BCR		47
#define GCC_PCNOC_BUS_TIMEOUT1_BCR		48
#define GCC_PCNOC_BUS_TIMEOUT2_BCR		49
#define GCC_PCNOC_BUS_TIMEOUT3_BCR		50
#define GCC_PCNOC_BUS_TIMEOUT4_BCR		51
#define GCC_PCNOC_BUS_TIMEOUT5_BCR		52
#define GCC_PCNOC_BUS_TIMEOUT6_BCR		53
#define GCC_PCNOC_BUS_TIMEOUT7_BCR		54
#define GCC_PCNOC_BUS_TIMEOUT8_BCR		55
#define GCC_PCNOC_BUS_TIMEOUT9_BCR		56
#define GCC_QPIC_BCR				57
#define GCC_SDCC_BCR				58
#define GCC_DCC_BCR				59
#define GCC_SPDM_BCR				60
#define GCC_MPM_BCR				61
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	62
#define GCC_RBCPR_BCR				63
#define GCC_CMN_BLK_BCR				64
#define GCC_TCSR_BCR				65
#define GCC_TLMM_BCR				66
#define GCC_QUPV3_AHB_MST_ARES			67
#define GCC_QUPV3_CORE_ARES			68
#define GCC_QUPV3_2X_CORE_ARES			69
#define GCC_QUPV3_SLEEP_ARES			70
#define GCC_QUPV3_AHB_SLV_ARES			71
#define GCC_QUPV3_I2C0_ARES			72
#define GCC_QUPV3_UART0_ARES			73
#define GCC_QUPV3_I2C1_ARES			74
#define GCC_QUPV3_UART1_ARES			75
#define GCC_QUPV3_SPI0_ARES			76
#define GCC_QUPV3_SPI1_ARES			77
#define GCC_DEBUG_ARES				78
#define GCC_GP1_ARES				79
#define GCC_GP2_ARES				80
#define GCC_GP3_ARES				81
#define GCC_IMEM_AXI_ARES			82
#define GCC_IMEM_CFG_AHB_ARES			83
#define GCC_TME_ARES				84
#define GCC_TME_TS_ARES				85
#define GCC_TME_SLOW_ARES			86
#define GCC_TME_RTC_TOGGLE_ARES			87

Annotation

Implementation Notes