include/dt-bindings/reset/qcom,ipq9574-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/reset/qcom,ipq9574-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/reset/qcom,ipq9574-gcc.h
Extension
.h
Size
5683 bytes
Lines
166
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H
#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H

#define GCC_ADSS_BCR						0
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			1
#define GCC_BLSP1_BCR						2
#define GCC_BLSP1_QUP1_BCR					3
#define GCC_BLSP1_QUP2_BCR					4
#define GCC_BLSP1_QUP3_BCR					5
#define GCC_BLSP1_QUP4_BCR					6
#define GCC_BLSP1_QUP5_BCR					7
#define GCC_BLSP1_QUP6_BCR					8
#define GCC_BLSP1_UART1_BCR					9
#define GCC_BLSP1_UART2_BCR					10
#define GCC_BLSP1_UART3_BCR					11
#define GCC_BLSP1_UART4_BCR					12
#define GCC_BLSP1_UART5_BCR					13
#define GCC_BLSP1_UART6_BCR					14
#define GCC_BOOT_ROM_BCR					15
#define GCC_MDIO_BCR						16
#define GCC_NSS_BCR						17
#define GCC_NSS_TBU_BCR						18
#define GCC_PCIE0_BCR						19
#define GCC_PCIE0_LINK_DOWN_BCR					20
#define GCC_PCIE0_PHY_BCR					21
#define GCC_PCIE0PHY_PHY_BCR					22
#define GCC_PCIE1_BCR						23
#define GCC_PCIE1_LINK_DOWN_BCR					24
#define GCC_PCIE1_PHY_BCR					25
#define GCC_PCIE1PHY_PHY_BCR					26
#define GCC_PCIE2_BCR						27
#define GCC_PCIE2_LINK_DOWN_BCR					28
#define GCC_PCIE2_PHY_BCR					29
#define GCC_PCIE2PHY_PHY_BCR					30
#define GCC_PCIE3_BCR						31
#define GCC_PCIE3_LINK_DOWN_BCR					32
#define GCC_PCIE3_PHY_BCR					33
#define GCC_PCIE3PHY_PHY_BCR					34
#define GCC_PRNG_BCR						35
#define GCC_QUSB2_0_PHY_BCR					36
#define GCC_SDCC_BCR						37
#define GCC_TLMM_BCR						38
#define GCC_UNIPHY0_BCR						39
#define GCC_UNIPHY1_BCR						40
#define GCC_UNIPHY2_BCR						41
#define GCC_USB0_PHY_BCR					42
#define GCC_USB3PHY_0_PHY_BCR					43
#define GCC_USB_BCR						44
#define GCC_ANOC0_TBU_BCR					45
#define GCC_ANOC1_TBU_BCR					46
#define GCC_ANOC_BCR						47
#define GCC_APSS_TCU_BCR					48
#define GCC_CMN_BLK_BCR						49
#define GCC_CMN_BLK_AHB_ARES					50
#define GCC_CMN_BLK_SYS_ARES					51
#define GCC_CMN_BLK_APU_ARES					52
#define GCC_DCC_BCR						53
#define GCC_DDRSS_BCR						54
#define GCC_IMEM_BCR						55
#define GCC_LPASS_BCR						56
#define GCC_MPM_BCR						57
#define GCC_MSG_RAM_BCR						58
#define GCC_NSSNOC_MEMNOC_1_ARES				59
#define GCC_NSSNOC_PCNOC_1_ARES					60
#define GCC_NSSNOC_SNOC_1_ARES					61
#define GCC_NSSNOC_XO_DCD_ARES					62
#define GCC_NSSNOC_TS_ARES					63
#define GCC_NSSCC_ARES						64
#define GCC_NSSNOC_NSSCC_ARES					65
#define GCC_NSSNOC_ATB_ARES					66
#define GCC_NSSNOC_MEMNOC_ARES					67
#define GCC_NSSNOC_QOSGEN_REF_ARES				68
#define GCC_NSSNOC_SNOC_ARES					69
#define GCC_NSSNOC_TIMEOUT_REF_ARES				70
#define GCC_NSS_CFG_ARES					71
#define GCC_UBI0_DBG_ARES					72
#define GCC_PCIE0_AHB_ARES					73
#define GCC_PCIE0_AUX_ARES					74
#define GCC_PCIE0_AXI_M_ARES					75
#define GCC_PCIE0_AXI_M_STICKY_ARES				76
#define GCC_PCIE0_AXI_S_ARES					77
#define GCC_PCIE0_AXI_S_STICKY_ARES				78
#define GCC_PCIE0_CORE_STICKY_ARES				79
#define GCC_PCIE0_PIPE_ARES					80
#define GCC_PCIE1_AHB_ARES					81
#define GCC_PCIE1_AUX_ARES					82
#define GCC_PCIE1_AXI_M_ARES					83
#define GCC_PCIE1_AXI_M_STICKY_ARES				84
#define GCC_PCIE1_AXI_S_ARES					85
#define GCC_PCIE1_AXI_S_STICKY_ARES				86

Annotation

Implementation Notes