include/dt-bindings/reset/qcom,ipq9650-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/reset/qcom,ipq9650-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/reset/qcom,ipq9650-gcc.h
Extension
.h
Size
8173 bytes
Lines
216
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H
#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H

#define GCC_ADSS_BCR						0
#define GCC_ADSS_PWM_CLK_ARES					1
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			2
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES		3
#define GCC_APSS_AHB_CLK_ARES					4
#define GCC_APSS_ATB_CLK_ARES					5
#define GCC_APSS_AXI_CLK_ARES					6
#define GCC_APSS_TS_CLK_ARES					7
#define GCC_BOOT_ROM_AHB_CLK_ARES				8
#define GCC_BOOT_ROM_BCR					9
#define GCC_CMN_12GPLL_AHB_CLK_ARES				10
#define GCC_CMN_12GPLL_APU_CLK_ARES				11
#define GCC_CMN_12GPLL_SYS_CLK_ARES				12
#define GCC_CMN_BLK_BCR						13
#define GCC_CMN_LDO_CLK_ARES					14
#define GCC_CPUSS_TRIG_CLK_ARES					15
#define GCC_GP1_CLK_ARES					16
#define GCC_GP2_CLK_ARES					17
#define GCC_GP3_CLK_ARES					18
#define GCC_MDIO_AHB_CLK_ARES					19
#define GCC_MDIO_BCR						20
#define GCC_NSSCC_CLK_ARES					21
#define GCC_NSSCFG_CLK_ARES					22
#define GCC_NSSNOC_ATB_CLK_ARES					23
#define GCC_NSSNOC_MEMNOC_1_CLK_ARES				24
#define GCC_NSSNOC_MEMNOC_CLK_ARES				25
#define GCC_NSSNOC_NSSCC_CLK_ARES				26
#define GCC_NSSNOC_PCNOC_1_CLK_ARES				27
#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES				28
#define GCC_NSSNOC_SNOC_1_CLK_ARES				29
#define GCC_NSSNOC_SNOC_CLK_ARES				30
#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES				31
#define GCC_NSSNOC_XO_DCD_CLK_ARES				32
#define GCC_NSS_BCR						33
#define GCC_NSS_TS_CLK_ARES					34
#define GCC_PCIE0PHY_PHY_BCR					35
#define GCC_PCIE0_AHB_CLK_ARES					36
#define GCC_PCIE0_AHB_RESET					37
#define GCC_PCIE0_AUX_CLK_ARES					38
#define GCC_PCIE0_AUX_RESET					39
#define GCC_PCIE0_AXI_M_CLK_ARES				40
#define GCC_PCIE0_AXI_M_RESET					41
#define GCC_PCIE0_AXI_M_STICKY_RESET				42
#define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES				43
#define GCC_PCIE0_AXI_S_CLK_ARES				44
#define GCC_PCIE0_AXI_S_RESET					45
#define GCC_PCIE0_AXI_S_STICKY_RESET				46
#define GCC_PCIE0_BCR						47
#define GCC_PCIE0_CORE_STICKY_RESET				48
#define GCC_PCIE0_LINK_DOWN_BCR					49
#define GCC_PCIE0_PHY_BCR					50
#define GCC_PCIE0_PIPE_CLK_ARES					51
#define GCC_PCIE0_PIPE_RESET					52
#define GCC_PCIE1PHY_PHY_BCR					53
#define GCC_PCIE1_AHB_CLK_ARES					54
#define GCC_PCIE1_AHB_RESET					55
#define GCC_PCIE1_AUX_CLK_ARES					56
#define GCC_PCIE1_AUX_RESET					57
#define GCC_PCIE1_AXI_M_CLK_ARES				58
#define GCC_PCIE1_AXI_M_RESET					59
#define GCC_PCIE1_AXI_M_STICKY_RESET				60
#define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES				61
#define GCC_PCIE1_AXI_S_CLK_ARES				62
#define GCC_PCIE1_AXI_S_RESET					63
#define GCC_PCIE1_AXI_S_STICKY_RESET				64
#define GCC_PCIE1_BCR						65
#define GCC_PCIE1_CORE_STICKY_RESET				66
#define GCC_PCIE1_LINK_DOWN_BCR					67
#define GCC_PCIE1_PHY_BCR					68
#define GCC_PCIE1_PIPE_CLK_ARES					69
#define GCC_PCIE1_PIPE_RESET					70
#define GCC_PCIE2PHY_PHY_BCR					71
#define GCC_PCIE2_AHB_CLK_ARES					72
#define GCC_PCIE2_AHB_RESET					73
#define GCC_PCIE2_AUX_CLK_ARES					74
#define GCC_PCIE2_AUX_RESET					75
#define GCC_PCIE2_AXI_M_CLK_ARES				76
#define GCC_PCIE2_AXI_M_RESET					77
#define GCC_PCIE2_AXI_M_STICKY_RESET				78
#define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES				79
#define GCC_PCIE2_AXI_S_CLK_ARES				80
#define GCC_PCIE2_AXI_S_RESET					81
#define GCC_PCIE2_AXI_S_STICKY_RESET				82
#define GCC_PCIE2_BCR						83
#define GCC_PCIE2_CORE_STICKY_RESET				84
#define GCC_PCIE2_LINK_DOWN_BCR					85
#define GCC_PCIE2_PHY_BCR					86

Annotation

Implementation Notes