include/dt-bindings/reset/rockchip,rk3562-cru.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/reset/rockchip,rk3562-cru.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/reset/rockchip,rk3562-cru.h- Extension
.h- Size
- 11211 bytes
- Lines
- 359
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
/********Name=SOFTRST_CON01,Offset=0x404********/
#define SRST_A_TOP_BIU 0
#define SRST_A_TOP_VIO_BIU 1
#define SRST_REF_PVTPLL_LOGIC 2
/********Name=SOFTRST_CON03,Offset=0x40C********/
#define SRST_NCOREPORESET0 3
#define SRST_NCOREPORESET1 4
#define SRST_NCOREPORESET2 5
#define SRST_NCOREPORESET3 6
#define SRST_NCORESET0 7
#define SRST_NCORESET1 8
#define SRST_NCORESET2 9
#define SRST_NCORESET3 10
#define SRST_NL2RESET 11
/********Name=SOFTRST_CON04,Offset=0x410********/
#define SRST_DAP 12
#define SRST_P_DBG_DAPLITE 13
#define SRST_REF_PVTPLL_CORE 14
/********Name=SOFTRST_CON05,Offset=0x414********/
#define SRST_A_CORE_BIU 15
#define SRST_P_CORE_BIU 16
#define SRST_H_CORE_BIU 17
/********Name=SOFTRST_CON06,Offset=0x418********/
#define SRST_A_NPU_BIU 18
#define SRST_H_NPU_BIU 19
#define SRST_A_RKNN 20
#define SRST_H_RKNN 21
#define SRST_REF_PVTPLL_NPU 22
/********Name=SOFTRST_CON08,Offset=0x420********/
#define SRST_A_GPU_BIU 23
#define SRST_GPU 24
#define SRST_REF_PVTPLL_GPU 25
#define SRST_GPU_BRG_BIU 26
/********Name=SOFTRST_CON09,Offset=0x424********/
#define SRST_RKVENC_CORE 27
#define SRST_A_VEPU_BIU 28
#define SRST_H_VEPU_BIU 29
#define SRST_A_RKVENC 30
#define SRST_H_RKVENC 31
/********Name=SOFTRST_CON10,Offset=0x428********/
#define SRST_RKVDEC_HEVC_CA 32
#define SRST_A_VDPU_BIU 33
#define SRST_H_VDPU_BIU 34
#define SRST_A_RKVDEC 35
#define SRST_H_RKVDEC 36
/********Name=SOFTRST_CON11,Offset=0x42C********/
#define SRST_A_VI_BIU 37
#define SRST_H_VI_BIU 38
#define SRST_P_VI_BIU 39
#define SRST_ISP 40
#define SRST_A_VICAP 41
#define SRST_H_VICAP 42
#define SRST_D_VICAP 43
#define SRST_I0_VICAP 44
#define SRST_I1_VICAP 45
#define SRST_I2_VICAP 46
#define SRST_I3_VICAP 47
/********Name=SOFTRST_CON12,Offset=0x430********/
#define SRST_P_CSIHOST0 48
#define SRST_P_CSIHOST1 49
#define SRST_P_CSIHOST2 50
#define SRST_P_CSIHOST3 51
#define SRST_P_CSIPHY0 52
#define SRST_P_CSIPHY1 53
/********Name=SOFTRST_CON13,Offset=0x434********/
#define SRST_A_VO_BIU 54
#define SRST_H_VO_BIU 55
#define SRST_A_VOP 56
#define SRST_H_VOP 57
#define SRST_D_VOP 58
#define SRST_D_VOP1 59
/********Name=SOFTRST_CON14,Offset=0x438********/
#define SRST_A_RGA_BIU 60
#define SRST_H_RGA_BIU 61
#define SRST_A_RGA 62
#define SRST_H_RGA 63
#define SRST_RGA_CORE 64
#define SRST_A_JDEC 65
#define SRST_H_JDEC 66
/********Name=SOFTRST_CON15,Offset=0x43C********/
#define SRST_B_EBK_BIU 67
#define SRST_P_EBK_BIU 68
#define SRST_AHB2AXI_EBC 69
#define SRST_H_EBC 70
#define SRST_D_EBC 71
#define SRST_H_EINK 72
#define SRST_P_EINK 73
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.