include/dt-bindings/reset/thead,th1520-reset.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/reset/thead,th1520-reset.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/reset/thead,th1520-reset.h
Extension
.h
Size
8382 bytes
Lines
237
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_TH1520_RESET_H
#define _DT_BINDINGS_TH1520_RESET_H

/* AO Subsystem */
#define TH1520_RESET_ID_SYSTEM		0
#define TH1520_RESET_ID_RTC_APB		1
#define TH1520_RESET_ID_RTC_REF		2
#define TH1520_RESET_ID_AOGPIO_DB	3
#define TH1520_RESET_ID_AOGPIO_APB	4
#define TH1520_RESET_ID_AOI2C_APB	5
#define TH1520_RESET_ID_PVT_APB		6
#define TH1520_RESET_ID_E902_CORE	7
#define TH1520_RESET_ID_E902_HAD	8
#define TH1520_RESET_ID_AOTIMER_APB	9
#define TH1520_RESET_ID_AOTIMER_CORE	10
#define TH1520_RESET_ID_AOWDT_APB	11
#define TH1520_RESET_ID_APSYS		12
#define TH1520_RESET_ID_NPUSYS		13
#define TH1520_RESET_ID_DDRSYS		14
#define TH1520_RESET_ID_AXI_AP2CP	15
#define TH1520_RESET_ID_AXI_CP2AP	16
#define TH1520_RESET_ID_AXI_CP2SRAM	17
#define TH1520_RESET_ID_AUDSYS_CORE	18
#define TH1520_RESET_ID_AUDSYS_IOPMP	19
#define TH1520_RESET_ID_AUDSYS		20
#define TH1520_RESET_ID_DSP0		21
#define TH1520_RESET_ID_DSP1		22
#define TH1520_RESET_ID_GPU_MODULE	23
#define TH1520_RESET_ID_VDEC		24
#define TH1520_RESET_ID_VENC		25
#define TH1520_RESET_ID_ADC_APB		26
#define TH1520_RESET_ID_AUDGPIO_DB	27
#define TH1520_RESET_ID_AUDGPIO_APB	28
#define TH1520_RESET_ID_AOUART_IF	29
#define TH1520_RESET_ID_AOUART_APB	30
#define TH1520_RESET_ID_SRAM_AXI_P0	31
#define TH1520_RESET_ID_SRAM_AXI_P1	32
#define TH1520_RESET_ID_SRAM_AXI_P2	33
#define TH1520_RESET_ID_SRAM_AXI_P3	34
#define TH1520_RESET_ID_SRAM_AXI_P4	35
#define TH1520_RESET_ID_SRAM_AXI_CORE	36
#define TH1520_RESET_ID_SE		37

/* AP Subsystem */
#define TH1520_RESET_ID_BROM			0
#define TH1520_RESET_ID_C910_TOP		1
#define TH1520_RESET_ID_NPU			2
#define TH1520_RESET_ID_WDT0			3
#define TH1520_RESET_ID_WDT1			4
#define TH1520_RESET_ID_C910_C0			5
#define TH1520_RESET_ID_C910_C1			6
#define TH1520_RESET_ID_C910_C2			7
#define TH1520_RESET_ID_C910_C3			8
#define TH1520_RESET_ID_CHIP_DBG_CORE		9
#define TH1520_RESET_ID_CHIP_DBG_AXI		10
#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI	11
#define TH1520_RESET_ID_AXI4_CPUSYS2_APB	12
#define TH1520_RESET_ID_X2H_CPUSYS		13
#define TH1520_RESET_ID_AHB2_CPUSYS		14
#define TH1520_RESET_ID_APB3_CPUSYS		15
#define TH1520_RESET_ID_MBOX0_APB		16
#define TH1520_RESET_ID_MBOX1_APB		17
#define TH1520_RESET_ID_MBOX2_APB		18
#define TH1520_RESET_ID_MBOX3_APB		19
#define TH1520_RESET_ID_TIMER0_APB		20
#define TH1520_RESET_ID_TIMER0_CORE		21
#define TH1520_RESET_ID_TIMER1_APB		22
#define TH1520_RESET_ID_TIMER1_CORE		23
#define TH1520_RESET_ID_PERISYS_AHB		24
#define TH1520_RESET_ID_PERISYS_APB1		25
#define TH1520_RESET_ID_PERISYS_APB2		26
#define TH1520_RESET_ID_GMAC0_APB		27
#define TH1520_RESET_ID_GMAC0_AHB		28
#define TH1520_RESET_ID_GMAC0_CLKGEN		29
#define TH1520_RESET_ID_GMAC0_AXI		30
#define TH1520_RESET_ID_UART0_APB		31
#define TH1520_RESET_ID_UART0_IF		32
#define TH1520_RESET_ID_UART1_APB		33
#define TH1520_RESET_ID_UART1_IF		34
#define TH1520_RESET_ID_UART2_APB		35
#define TH1520_RESET_ID_UART2_IF		36
#define TH1520_RESET_ID_UART3_APB		37
#define TH1520_RESET_ID_UART3_IF		38
#define TH1520_RESET_ID_UART4_APB		39
#define TH1520_RESET_ID_UART4_IF		40
#define TH1520_RESET_ID_UART5_APB		41
#define TH1520_RESET_ID_UART5_IF		42
#define TH1520_RESET_ID_QSPI0_IF		43
#define TH1520_RESET_ID_QSPI0_APB		44
#define TH1520_RESET_ID_QSPI1_IF		45

Annotation

Implementation Notes