include/linux/bnge/hsi.h
Source file repositories/reference/linux-study-clean/include/linux/bnge/hsi.h
File Facts
- System
- Linux kernel
- Corpus path
include/linux/bnge/hsi.h- Extension
.h- Size
- 545804 bytes
- Lines
- 12610
- Domain
- Core OS
- Bucket
- Core Kernel Interface
- Inferred role
- Core OS: implementation source
- Status
- source implementation candidate
Why This File Exists
Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct hwrm_cmd_hdrstruct hwrm_resp_hdrstruct tlvstruct inputstruct outputstruct hwrm_short_inputstruct cmd_numsstruct ret_codesstruct hwrm_err_outputstruct hwrm_ver_get_inputstruct hwrm_ver_get_outputstruct eject_cmplstruct hwrm_cmplstruct hwrm_fwd_req_cmplstruct hwrm_fwd_resp_cmplstruct hwrm_async_event_cmplstruct hwrm_async_event_cmpl_link_status_changestruct hwrm_async_event_cmpl_port_conn_not_allowedstruct hwrm_async_event_cmpl_link_speed_cfg_changestruct hwrm_async_event_cmpl_reset_notifystruct hwrm_async_event_cmpl_error_recoverystruct hwrm_async_event_cmpl_ring_monitor_msgstruct hwrm_async_event_cmpl_vf_cfg_changestruct hwrm_async_event_cmpl_default_vnic_changestruct hwrm_async_event_cmpl_hw_flow_agedstruct hwrm_async_event_cmpl_eem_cache_flush_reqstruct hwrm_async_event_cmpl_eem_cache_flush_donestruct hwrm_async_event_cmpl_deferred_responsestruct hwrm_async_event_cmpl_echo_requeststruct hwrm_async_event_cmpl_phc_updatestruct hwrm_async_event_cmpl_pps_timestampstruct hwrm_async_event_cmpl_error_reportstruct hwrm_async_event_cmpl_dbg_buf_producerstruct hwrm_async_event_cmpl_hwrm_errorstruct hwrm_async_event_cmpl_error_report_basestruct hwrm_async_event_cmpl_error_report_pause_stormstruct hwrm_async_event_cmpl_error_report_invalid_signalstruct hwrm_async_event_cmpl_error_report_nvmstruct hwrm_async_event_cmpl_error_report_doorbell_drop_thresholdstruct hwrm_async_event_cmpl_error_report_thermalstruct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supportedstruct hwrm_func_reset_inputstruct hwrm_func_reset_outputstruct hwrm_func_getfid_inputstruct hwrm_func_getfid_outputstruct hwrm_func_vf_alloc_inputstruct hwrm_func_vf_alloc_outputstruct hwrm_func_vf_free_input
Annotated Snippet
struct hwrm_cmd_hdr {
__le16 req_type;
__le16 cmpl_ring;
__le16 seq_id;
__le16 target_id;
__le64 resp_addr;
};
/* hwrm_resp_hdr (size:64b/8B) */
struct hwrm_resp_hdr {
__le16 error_code;
__le16 req_type;
__le16 seq_id;
__le16 resp_len;
};
#define CMD_DISCR_TLV_ENCAP 0x8000UL
#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
#define TLV_TYPE_HWRM_REQUEST 0x1UL
#define TLV_TYPE_HWRM_RESPONSE 0x2UL
#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT 0x8UL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT 0x9UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT 0xaUL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT 0xbUL
#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
/* tlv (size:64b/8B) */
struct tlv {
__le16 cmd_discr;
u8 reserved_8b;
u8 flags;
#define TLV_FLAGS_MORE 0x1UL
#define TLV_FLAGS_MORE_LAST 0x0UL
#define TLV_FLAGS_MORE_NOT_LAST 0x1UL
#define TLV_FLAGS_REQUIRED 0x2UL
#define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
#define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
#define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
__le16 tlv_type;
__le16 length;
};
/* input (size:128b/16B) */
struct input {
__le16 req_type;
__le16 cmpl_ring;
__le16 seq_id;
__le16 target_id;
__le64 resp_addr;
};
/* output (size:64b/8B) */
struct output {
__le16 error_code;
__le16 req_type;
__le16 seq_id;
__le16 resp_len;
};
/* hwrm_short_input (size:128b/16B) */
struct hwrm_short_input {
__le16 req_type;
__le16 signature;
#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
#define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
__le16 target_id;
#define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
#define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL
#define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS
__le16 size;
__le64 req_addr;
};
/* cmd_nums (size:64b/8B) */
struct cmd_nums {
Annotation
- Detected declarations: `struct hwrm_cmd_hdr`, `struct hwrm_resp_hdr`, `struct tlv`, `struct input`, `struct output`, `struct hwrm_short_input`, `struct cmd_nums`, `struct ret_codes`, `struct hwrm_err_output`, `struct hwrm_ver_get_input`.
- Atlas domain: Core OS / Core Kernel Interface.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.