include/linux/bnxt/ulp.h
Source file repositories/reference/linux-study-clean/include/linux/bnxt/ulp.h
File Facts
- System
- Linux kernel
- Corpus path
include/linux/bnxt/ulp.h- Extension
.h- Size
- 4066 bytes
- Lines
- 145
- Domain
- Core OS
- Bucket
- Core Kernel Interface
- Inferred role
- Core OS: implementation source
- Status
- source implementation candidate
Why This File Exists
Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/auxiliary_bus.h
Detected Declarations
struct hwrm_async_event_cmplstruct bnxtstruct bnxt_aux_privstruct bnxt_msix_entrystruct bnxt_ulp_opsstruct bnxt_fw_msgstruct bnxt_ulpstruct bnxt_en_devenum bnxt_auxdev_typefunction bnxt_ulp_registered
Annotated Snippet
struct bnxt_aux_priv {
struct auxiliary_device aux_dev;
struct bnxt_en_dev *edev;
int id;
};
struct bnxt_msix_entry {
u32 vector;
u32 ring_idx;
u32 db_offset;
};
struct bnxt_ulp_ops {
/* async_notifier() cannot sleep (in BH context) */
void (*ulp_async_notifier)(void *, struct hwrm_async_event_cmpl *);
void (*ulp_irq_stop)(void *, bool);
void (*ulp_irq_restart)(void *, struct bnxt_msix_entry *);
};
struct bnxt_fw_msg {
void *msg;
int msg_len;
void *resp;
int resp_max_len;
int timeout;
};
struct bnxt_ulp {
void *handle;
struct bnxt_ulp_ops __rcu *ulp_ops;
unsigned long *async_events_bmap;
u16 max_async_event_id;
u16 msix_requested;
};
struct bnxt_en_dev {
struct net_device *net;
struct pci_dev *pdev;
struct bnxt_msix_entry msix_entries[BNXT_MAX_ROCE_MSIX];
u32 flags;
#define BNXT_EN_FLAG_ROCEV1_CAP 0x1
#define BNXT_EN_FLAG_ROCEV2_CAP 0x2
#define BNXT_EN_FLAG_ROCE_CAP (BNXT_EN_FLAG_ROCEV1_CAP | \
BNXT_EN_FLAG_ROCEV2_CAP)
#define BNXT_EN_FLAG_ULP_STOPPED 0x8
#define BNXT_EN_FLAG_VF 0x10
#define BNXT_EN_VF(edev) ((edev)->flags & BNXT_EN_FLAG_VF)
#define BNXT_EN_FLAG_ROCE_VF_RES_MGMT 0x20
#define BNXT_EN_FLAG_SW_RES_LMT 0x40
#define BNXT_EN_SW_RES_LMT(edev) ((edev)->flags & BNXT_EN_FLAG_SW_RES_LMT)
struct bnxt_ulp *ulp_tbl;
int l2_db_size; /* Doorbell BAR size in
* bytes mapped by L2
* driver.
*/
int l2_db_size_nc; /* Doorbell BAR size in
* bytes mapped as non-
* cacheable.
*/
int l2_db_offset; /* Doorbell offset in
* bytes within
* l2_db_size_nc.
*/
u16 chip_num;
u16 hw_ring_stats_size;
u16 pf_port_id;
unsigned long en_state; /* Could be checked in
* RoCE driver suspend
* mode only. Will be
* updated in resume.
*/
void __iomem *bar0;
u16 ulp_num_msix_vec;
u16 ulp_num_ctxs;
/* serialize ulp operations */
struct mutex en_dev_lock;
};
static inline bool bnxt_ulp_registered(struct bnxt_en_dev *edev)
{
if (edev && rcu_access_pointer(edev->ulp_tbl->ulp_ops))
return true;
return false;
}
int bnxt_get_ulp_msix_num(struct bnxt *bp);
int bnxt_get_ulp_msix_num_in_use(struct bnxt *bp);
Annotation
- Immediate include surface: `linux/auxiliary_bus.h`.
- Detected declarations: `struct hwrm_async_event_cmpl`, `struct bnxt`, `struct bnxt_aux_priv`, `struct bnxt_msix_entry`, `struct bnxt_ulp_ops`, `struct bnxt_fw_msg`, `struct bnxt_ulp`, `struct bnxt_en_dev`, `enum bnxt_auxdev_type`, `function bnxt_ulp_registered`.
- Atlas domain: Core OS / Core Kernel Interface.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.