include/linux/clk/analogbits-wrpll-cln28hpc.h
Source file repositories/reference/linux-study-clean/include/linux/clk/analogbits-wrpll-cln28hpc.h
File Facts
- System
- Linux kernel
- Corpus path
include/linux/clk/analogbits-wrpll-cln28hpc.h- Extension
.h- Size
- 2875 bytes
- Lines
- 80
- Domain
- Core OS
- Bucket
- Core Kernel Interface
- Inferred role
- Core OS: implementation source
- Status
- source implementation candidate
Why This File Exists
Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.h
Detected Declarations
struct wrpll_cfg
Annotated Snippet
struct wrpll_cfg {
u8 divr;
u8 divq;
u8 range;
u8 flags;
u16 divf;
/* private: */
u32 output_rate_cache[DIVQ_VALUES];
unsigned long parent_rate;
u8 max_r;
u8 init_r;
};
int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
unsigned long parent_rate);
unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c);
unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
unsigned long parent_rate);
#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
Annotation
- Immediate include surface: `linux/types.h`.
- Detected declarations: `struct wrpll_cfg`.
- Atlas domain: Core OS / Core Kernel Interface.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.