include/linux/clk/renesas.h

Source file repositories/reference/linux-study-clean/include/linux/clk/renesas.h

File Facts

System
Linux kernel
Corpus path
include/linux/clk/renesas.h
Extension
.h
Size
4878 bytes
Lines
192
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rzv2h_pll_limits {
	struct {
		u32 min;
		u32 max;
	} fout;

	struct {
		u32 min;
		u32 max;
	} fvco;

	struct {
		u16 min;
		u16 max;
	} m;

	struct {
		u8 min;
		u8 max;
	} p;

	struct {
		u8 min;
		u8 max;
	} s;

	struct {
		s16 min;
		s16 max;
	} k;
};

/**
 * struct rzv2h_pll_pars - PLL configuration parameters
 *
 * This structure contains the configuration parameters for the
 * Phase-Locked Loop (PLL), used to achieve a specific output frequency.
 *
 * @m: Main divider value
 * @p: Pre-divider value
 * @s: Output divider value
 * @k: Delta-sigma modulation value
 * @freq_millihz: Calculated PLL output frequency in millihertz
 * @error_millihz: Frequency error from target in millihertz (signed)
 */
struct rzv2h_pll_pars {
	u16 m;
	u8 p;
	u8 s;
	s16 k;
	u64 freq_millihz;
	s64 error_millihz;
};

/**
 * struct rzv2h_pll_div_pars - PLL parameters with post-divider
 *
 * This structure is used for PLLs that include an additional post-divider
 * stage after the main PLL block. It contains both the PLL configuration
 * parameters and the resulting frequency/error values after the divider.
 *
 * @pll: Main PLL configuration parameters (see struct rzv2h_pll_pars)
 *
 * @div: Post-divider configuration and result
 * @div.divider_value: Divider applied to the PLL output
 * @div.freq_millihz: Output frequency after divider in millihertz
 * @div.error_millihz: Frequency error from target in millihertz (signed)
 */
struct rzv2h_pll_div_pars {
	struct rzv2h_pll_pars pll;
	struct {
		u8 divider_value;
		u64 freq_millihz;
		s64 error_millihz;
	} div;
};

#define RZV2H_CPG_PLL_DSI_LIMITS(name)					\
	static const struct rzv2h_pll_limits (name) = {			\
		.fout = { .min = 25 * MEGA, .max = 375 * MEGA },	\
		.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA },	\
		.m = { .min = 64, .max = 533 },				\
		.p = { .min = 1, .max = 4 },				\
		.s = { .min = 0, .max = 6 },				\
		.k = { .min = -32768, .max = 32767 },			\
	}								\

#ifdef CONFIG_CLK_RZV2H
bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
			struct rzv2h_pll_pars *pars, u64 freq_millihz);

Annotation

Implementation Notes