include/linux/irqchip/arm-gic-v5.h

Source file repositories/reference/linux-study-clean/include/linux/irqchip/arm-gic-v5.h

File Facts

System
Linux kernel
Corpus path
include/linux/irqchip/arm-gic-v5.h
Extension
.h
Size
12030 bytes
Lines
431
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

struct gicv5_chip_data {
	struct fwnode_handle	*fwnode;
	struct irq_domain	*ppi_domain;
	struct irq_domain	*spi_domain;
	struct irq_domain	*lpi_domain;
	struct irq_domain	*ipi_domain;
	u32			global_spi_count;
	u8			cpuif_pri_bits;
	u8			cpuif_id_bits;
	u8			irs_pri_bits;
	bool			virt_capable;
	struct {
		__le64 *l1ist_addr;
		u32 l2_size;
		u8 l2_bits;
		bool l2;
	} ist;
};

extern struct gicv5_chip_data gicv5_global_data __read_mostly;

struct gicv5_irs_chip_data {
	struct list_head	entry;
	struct fwnode_handle	*fwnode;
	void __iomem		*irs_base;
	u32			flags;
	u32			spi_min;
	u32			spi_range;
	raw_spinlock_t		spi_config_lock;
};

static inline int gicv5_wait_for_op_s_atomic(void __iomem *addr, u32 offset,
					     const char *reg_s, u32 mask,
					     u32 *val)
{
	void __iomem *reg = addr + offset;
	u32 tmp;
	int ret;

	ret = readl_poll_timeout_atomic(reg, tmp, tmp & mask, 1, 10 * USEC_PER_MSEC);
	if (unlikely(ret == -ETIMEDOUT)) {
		pr_err_ratelimited("%s timeout...\n", reg_s);
		return ret;
	}

	if (val)
		*val = tmp;

	return 0;
}

static inline int gicv5_wait_for_op_s(void __iomem *addr, u32 offset,
				      const char *reg_s, u32 mask)
{
	void __iomem *reg = addr + offset;
	u32 val;
	int ret;

	ret = readl_poll_timeout(reg, val, val & mask, 1, 10 * USEC_PER_MSEC);
	if (unlikely(ret == -ETIMEDOUT)) {
		pr_err_ratelimited("%s timeout...\n", reg_s);
		return ret;
	}

	return 0;
}

#define gicv5_wait_for_op_atomic(base, reg, mask, val) \
	gicv5_wait_for_op_s_atomic(base, reg, #reg, mask, val)

#define gicv5_wait_for_op(base, reg, mask) \
	gicv5_wait_for_op_s(base, reg, #reg, mask)

void __init gicv5_init_lpi_domain(void);
void __init gicv5_free_lpi_domain(void);

int gicv5_irs_of_probe(struct device_node *parent);
int gicv5_irs_acpi_probe(void);
void gicv5_irs_remove(void);
int gicv5_irs_enable(void);
void gicv5_irs_its_probe(void);
int gicv5_irs_register_cpu(int cpuid);
int gicv5_irs_cpu_to_iaffid(int cpu_id, u16 *iaffid);
struct gicv5_irs_chip_data *gicv5_irs_lookup_by_spi_id(u32 spi_id);
int gicv5_spi_irq_set_type(struct irq_data *d, unsigned int type);
int gicv5_irs_iste_alloc(u32 lpi);
void gicv5_irs_syncr(void);

/* Embedded in kvm.arch */
struct gicv5_vpe {

Annotation

Implementation Notes