include/linux/mfd/cs42l43-regs.h

Source file repositories/reference/linux-study-clean/include/linux/mfd/cs42l43-regs.h

File Facts

System: Linux kernel
Corpus path: include/linux/mfd/cs42l43-regs.h
Extension: .h
Size: 50016 bytes
Lines: 1261
Domain: Core OS
Bucket: Core Kernel Interface
Inferred role: Core OS: implementation source
Status: source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef CS42L43_CORE_REGS_H
#define CS42L43_CORE_REGS_H

/* Registers */
#define CS42L43_GEN_INT_STAT_1					0x000000C0
#define CS42L43_GEN_INT_MASK_1					0x000000C1
#define CS42L43_DEVID						0x00003000
#define CS42L43_REVID						0x00003004
#define CS42L43_RELID						0x0000300C
#define CS42L43_SFT_RESET					0x00003020
#define CS42L43_DRV_CTRL1					0x00006004
#define CS42L43_DRV_CTRL3					0x0000600C
#define CS42L43_DRV_CTRL4					0x00006010
#define CS42L43_DRV_CTRL_5					0x00006014
#define CS42L43_GPIO_CTRL1					0x00006034
#define CS42L43_GPIO_CTRL2					0x00006038
#define CS42L43_GPIO_STS					0x0000603C
#define CS42L43_GPIO_FN_SEL					0x00006040
#define CS42L43_MCLK_SRC_SEL					0x00007004
#define CS42L43_CCM_BLK_CLK_CONTROL				0x00007010
#define CS42L43_SAMPLE_RATE1					0x00007014
#define CS42L43_SAMPLE_RATE2					0x00007018
#define CS42L43_SAMPLE_RATE3					0x0000701C
#define CS42L43_SAMPLE_RATE4					0x00007020
#define CS42L43_PLL_CONTROL					0x00007034
#define CS42L43_FS_SELECT1					0x00007038
#define CS42L43_FS_SELECT2					0x0000703C
#define CS42L43_FS_SELECT3					0x00007040
#define CS42L43_FS_SELECT4					0x00007044
#define CS42L43_PDM_CONTROL					0x0000704C
#define CS42L43_ASP_CLK_CONFIG1					0x00007058
#define CS42L43_ASP_CLK_CONFIG2					0x0000705C
#define CS42L43_OSC_DIV_SEL					0x00007068
#define CS42L43_ADC_B_CTRL1					0x00008000
#define CS42L43_ADC_B_CTRL2					0x00008004
#define CS42L43_DECIM_HPF_WNF_CTRL1				0x0000803C
#define CS42L43_DECIM_HPF_WNF_CTRL2				0x00008040
#define CS42L43_DECIM_HPF_WNF_CTRL3				0x00008044
#define CS42L43_DECIM_HPF_WNF_CTRL4				0x00008048
#define CS42L43_DMIC_PDM_CTRL					0x0000804C
#define CS42L43_DECIM_VOL_CTRL_CH1_CH2				0x00008050
#define CS42L43_DECIM_VOL_CTRL_CH3_CH4				0x00008054
#define CS42L43_DECIM_VOL_CTRL_UPDATE				0x00008058
#define CS42L43_INTP_VOLUME_CTRL1				0x00009008
#define CS42L43_INTP_VOLUME_CTRL2				0x0000900C
#define CS42L43_AMP1_2_VOL_RAMP					0x00009010
#define CS42L43_ASP_CTRL					0x0000A000
#define CS42L43_ASP_FSYNC_CTRL1					0x0000A004
#define CS42L43_ASP_FSYNC_CTRL2					0x0000A008
#define CS42L43_ASP_FSYNC_CTRL3					0x0000A00C
#define CS42L43_ASP_FSYNC_CTRL4					0x0000A010
#define CS42L43_ASP_DATA_CTRL					0x0000A018
#define CS42L43_ASP_RX_EN					0x0000A020
#define CS42L43_ASP_TX_EN					0x0000A024
#define CS42L43_ASP_RX_CH1_CTRL					0x0000A028
#define CS42L43_ASP_RX_CH2_CTRL					0x0000A02C
#define CS42L43_ASP_RX_CH3_CTRL					0x0000A030
#define CS42L43_ASP_RX_CH4_CTRL					0x0000A034
#define CS42L43_ASP_RX_CH5_CTRL					0x0000A038
#define CS42L43_ASP_RX_CH6_CTRL					0x0000A03C
#define CS42L43_ASP_TX_CH1_CTRL					0x0000A068
#define CS42L43_ASP_TX_CH2_CTRL					0x0000A06C
#define CS42L43_ASP_TX_CH3_CTRL					0x0000A070
#define CS42L43_ASP_TX_CH4_CTRL					0x0000A074
#define CS42L43_ASP_TX_CH5_CTRL					0x0000A078
#define CS42L43_ASP_TX_CH6_CTRL					0x0000A07C
#define CS42L43_OTP_REVISION_ID					0x0000B02C
#define CS42L43_ASPTX1_INPUT					0x0000C200
#define CS42L43_ASPTX2_INPUT					0x0000C210
#define CS42L43_ASPTX3_INPUT					0x0000C220
#define CS42L43_ASPTX4_INPUT					0x0000C230
#define CS42L43_ASPTX5_INPUT					0x0000C240
#define CS42L43_ASPTX6_INPUT					0x0000C250
#define CS42L43_SWIRE_DP1_CH1_INPUT				0x0000C280
#define CS42L43_SWIRE_DP1_CH2_INPUT				0x0000C290
#define CS42L43_SWIRE_DP1_CH3_INPUT				0x0000C2A0
#define CS42L43_SWIRE_DP1_CH4_INPUT				0x0000C2B0
#define CS42L43_SWIRE_DP2_CH1_INPUT				0x0000C2C0
#define CS42L43_SWIRE_DP2_CH2_INPUT				0x0000C2D0
#define CS42L43_SWIRE_DP3_CH1_INPUT				0x0000C2E0
#define CS42L43_SWIRE_DP3_CH2_INPUT				0x0000C2F0
#define CS42L43_SWIRE_DP4_CH1_INPUT				0x0000C300
#define CS42L43_SWIRE_DP4_CH2_INPUT				0x0000C310
#define CS42L43_ASRC_INT1_INPUT1				0x0000C400
#define CS42L43_ASRC_INT2_INPUT1				0x0000C410
#define CS42L43_ASRC_INT3_INPUT1				0x0000C420
#define CS42L43_ASRC_INT4_INPUT1				0x0000C430
#define CS42L43_ASRC_DEC1_INPUT1				0x0000C440
#define CS42L43_ASRC_DEC2_INPUT1				0x0000C450
#define CS42L43_ASRC_DEC3_INPUT1				0x0000C460

Annotation

Atlas domain: Core OS / Core Kernel Interface.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.