include/linux/mfd/max77705-private.h

Source file repositories/reference/linux-study-clean/include/linux/mfd/max77705-private.h

File Facts

System
Linux kernel
Corpus path
include/linux/mfd/max77705-private.h
Extension
.h
Size
5647 bytes
Lines
196
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __LINUX_MFD_MAX77705_PRIV_H
#define __LINUX_MFD_MAX77705_PRIV_H

#define MAX77705_SRC_IRQ_CHG	BIT(0)
#define MAX77705_SRC_IRQ_TOP	BIT(1)
#define MAX77705_SRC_IRQ_FG	BIT(2)
#define MAX77705_SRC_IRQ_USBC	BIT(3)
#define MAX77705_SRC_IRQ_ALL	(MAX77705_SRC_IRQ_CHG | MAX77705_SRC_IRQ_TOP | \
				MAX77705_SRC_IRQ_FG | MAX77705_SRC_IRQ_USBC)

/* MAX77705_PMIC_REG_PMICREV register */
#define MAX77705_VERSION_SHIFT	3
#define MAX77705_REVISION_MASK	GENMASK(2, 0)
#define MAX77705_VERSION_MASK	GENMASK(7, MAX77705_VERSION_SHIFT)
/* MAX77705_PMIC_REG_MAINCTRL1 register */
#define MAX77705_MAINCTRL1_BIASEN_SHIFT	7
#define MAX77705_MAINCTRL1_BIASEN_MASK	BIT(MAX77705_MAINCTRL1_BIASEN_SHIFT)
/* MAX77705_PMIC_REG_MCONFIG2 (haptics) register */
#define MAX77705_CONFIG2_MEN_SHIFT	6
#define MAX77705_CONFIG2_MODE_SHIFT	7
#define MAX77705_CONFIG2_HTYP_SHIFT	5
/* MAX77705_PMIC_REG_SYSTEM_INT_MASK register */
#define MAX77705_SYSTEM_IRQ_BSTEN_INT	BIT(3)
#define MAX77705_SYSTEM_IRQ_SYSUVLO_INT	BIT(4)
#define MAX77705_SYSTEM_IRQ_SYSOVLO_INT	BIT(5)
#define MAX77705_SYSTEM_IRQ_TSHDN_INT	BIT(6)
#define MAX77705_SYSTEM_IRQ_TM_INT	BIT(7)
/* MAX77705_RGBLED_REG_LEDEN register */
#define MAX77705_RGBLED_EN_WIDTH	2
/* MAX77705_RGBLED_REG_LEDBLNK register */
#define MAX77705_RGB_DELAY_100_STEP_LIM 500
#define MAX77705_RGB_DELAY_100_STEP_COUNT 4
#define MAX77705_RGB_DELAY_100_STEP 100
#define MAX77705_RGB_DELAY_250_STEP_LIM 3250
#define MAX77705_RGB_DELAY_250_STEP 250
#define MAX77705_RGB_DELAY_500_STEP 500
#define MAX77705_RGB_DELAY_500_STEP_COUNT 10
#define MAX77705_RGB_DELAY_500_STEP_LIM 5000
#define MAX77705_RGB_DELAY_1000_STEP_LIM 8000
#define MAX77705_RGB_DELAY_1000_STEP_COUNT 13
#define MAX77705_RGB_DELAY_1000_STEP 1000
#define MAX77705_RGB_DELAY_2000_STEP 2000
#define MAX77705_RGB_DELAY_2000_STEP_COUNT 13
#define MAX77705_RGB_DELAY_2000_STEP_LIM 12000

enum max77705_hw_rev {
	MAX77705_PASS1 = 1,
	MAX77705_PASS2,
	MAX77705_PASS3
};

enum max77705_reg {
	MAX77705_PMIC_REG_PMICID1		= 0x00,
	MAX77705_PMIC_REG_PMICREV		= 0x01,
	MAX77705_PMIC_REG_MAINCTRL1		= 0x02,
	MAX77705_PMIC_REG_BSTOUT_MASK		= 0x03,
	MAX77705_PMIC_REG_FORCE_EN_MASK		= 0x08,
	MAX77705_PMIC_REG_MCONFIG		= 0x10,
	MAX77705_PMIC_REG_MCONFIG2		= 0x11,
	MAX77705_PMIC_REG_INTSRC		= 0x22,
	MAX77705_PMIC_REG_INTSRC_MASK		= 0x23,
	MAX77705_PMIC_REG_SYSTEM_INT		= 0x24,
	MAX77705_PMIC_REG_RESERVED_25		= 0x25,
	MAX77705_PMIC_REG_SYSTEM_INT_MASK	= 0x26,
	MAX77705_PMIC_REG_RESERVED_27		= 0x27,
	MAX77705_PMIC_REG_RESERVED_28		= 0x28,
	MAX77705_PMIC_REG_RESERVED_29		= 0x29,
	MAX77705_PMIC_REG_BOOSTCONTROL1		= 0x4C,
	MAX77705_PMIC_REG_BOOSTCONTROL2		= 0x4F,
	MAX77705_PMIC_REG_SW_RESET		= 0x50,
	MAX77705_PMIC_REG_USBC_RESET		= 0x51,

	MAX77705_PMIC_REG_END
};

enum max77705_chg_reg {
	MAX77705_CHG_REG_BASE			= 0xB0,
	MAX77705_CHG_REG_INT			= 0,
	MAX77705_CHG_REG_INT_MASK,
	MAX77705_CHG_REG_INT_OK,
	MAX77705_CHG_REG_DETAILS_00,
	MAX77705_CHG_REG_DETAILS_01,
	MAX77705_CHG_REG_DETAILS_02,
	MAX77705_CHG_REG_DTLS_03,
	MAX77705_CHG_REG_CNFG_00,
	MAX77705_CHG_REG_CNFG_01,
	MAX77705_CHG_REG_CNFG_02,
	MAX77705_CHG_REG_CNFG_03,
	MAX77705_CHG_REG_CNFG_04,
	MAX77705_CHG_REG_CNFG_05,

Annotation

Implementation Notes