include/linux/mfd/rohm-bd96801.h
Source file repositories/reference/linux-study-clean/include/linux/mfd/rohm-bd96801.h
File Facts
- System
- Linux kernel
- Corpus path
include/linux/mfd/rohm-bd96801.h- Extension
.h- Size
- 5928 bytes
- Lines
- 218
- Domain
- Core OS
- Bucket
- Core Kernel Interface
- Inferred role
- Core OS: implementation source
- Status
- source implementation candidate
Why This File Exists
Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __MFD_BD96801_H__
#define __MFD_BD96801_H__
#define BD96801_REG_SSCG_CTRL 0x09
#define BD96801_REG_SHD_INTB 0x20
#define BD96801_LDO5_VOL_LVL_REG 0x2c
#define BD96801_LDO6_VOL_LVL_REG 0x2d
#define BD96801_LDO7_VOL_LVL_REG 0x2e
#define BD96801_REG_BUCK_OVP 0x30
#define BD96801_REG_BUCK_OVD 0x35
#define BD96801_REG_LDO_OVP 0x31
#define BD96801_REG_LDO_OVD 0x36
#define BD96801_REG_BOOT_OVERTIME 0x3a
#define BD96801_REG_WD_TMO 0x40
#define BD96801_REG_WD_CONF 0x41
#define BD96801_REG_WD_FEED 0x42
#define BD96801_REG_WD_FAILCOUNT 0x43
#define BD96801_REG_WD_ASK 0x46
#define BD96801_REG_WD_STATUS 0x4a
#define BD96801_REG_PMIC_STATE 0x4f
#define BD96801_REG_EXT_STATE 0x50
#define BD96801_STATE_STBY 0x09
#define BD96801_LOCK_REG 0x04
#define BD96801_UNLOCK 0x9d
#define BD96801_LOCK 0x00
/* IRQ register area */
#define BD96801_REG_INT_MAIN 0x51
/*
* The BD96801 has two physical IRQ lines, INTB and ERRB.
*
* The 'main status register' is located at 0x51.
* The ERRB status registers are located at 0x52 ... 0x5B
* INTB status registers are at range 0x5c ... 0x63
*/
#define BD96801_REG_INT_SYS_ERRB1 0x52
#define BD96801_REG_INT_BUCK2_ERRB 0x56
#define BD96801_REG_INT_SYS_INTB 0x5c
#define BD96801_REG_INT_BUCK2_INTB 0x5e
#define BD96801_REG_INT_LDO7_INTB 0x63
/* MASK registers */
#define BD96801_REG_MASK_SYS_INTB 0x73
#define BD96801_REG_MASK_SYS_ERRB 0x69
#define BD96801_MAX_REGISTER 0x7a
#define BD96801_OTP_ERR_MASK BIT(0)
#define BD96801_DBIST_ERR_MASK BIT(1)
#define BD96801_EEP_ERR_MASK BIT(2)
#define BD96801_ABIST_ERR_MASK BIT(3)
#define BD96801_PRSTB_ERR_MASK BIT(4)
#define BD96801_DRMOS1_ERR_MASK BIT(5)
#define BD96801_DRMOS2_ERR_MASK BIT(6)
#define BD96801_SLAVE_ERR_MASK BIT(7)
#define BD96801_VREF_ERR_MASK BIT(0)
#define BD96801_TSD_ERR_MASK BIT(1)
#define BD96801_UVLO_ERR_MASK BIT(2)
#define BD96801_OVLO_ERR_MASK BIT(3)
#define BD96801_OSC_ERR_MASK BIT(4)
#define BD96801_PON_ERR_MASK BIT(5)
#define BD96801_POFF_ERR_MASK BIT(6)
#define BD96801_CMD_SHDN_ERR_MASK BIT(7)
#define BD96801_INT_PRSTB_WDT_ERR_MASK BIT(0)
#define BD96801_INT_CHIP_IF_ERR_MASK BIT(3)
#define BD96801_INT_SHDN_ERR_MASK BIT(7)
#define BD96801_OUT_PVIN_ERR_MASK BIT(0)
#define BD96801_OUT_OVP_ERR_MASK BIT(1)
#define BD96801_OUT_UVP_ERR_MASK BIT(2)
#define BD96801_OUT_SHDN_ERR_MASK BIT(7)
/* ERRB IRQs */
enum {
/* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
BD96801_OTP_ERR_STAT,
BD96801_DBIST_ERR_STAT,
BD96801_EEP_ERR_STAT,
BD96801_ABIST_ERR_STAT,
BD96801_PRSTB_ERR_STAT,
BD96801_DRMOS1_ERR_STAT,
BD96801_DRMOS2_ERR_STAT,
BD96801_SLAVE_ERR_STAT,
BD96801_VREF_ERR_STAT,
BD96801_TSD_ERR_STAT,
BD96801_UVLO_ERR_STAT,
BD96801_OVLO_ERR_STAT,
BD96801_OSC_ERR_STAT,
Annotation
- Atlas domain: Core OS / Core Kernel Interface.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.