include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

Source file repositories/reference/linux-study-clean/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

File Facts

System
Linux kernel
Corpus path
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
Extension
.h
Size
21991 bytes
Lines
473
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
#define __LINUX_IMX6Q_IOMUXC_GPR_H

#include <linux/bitops.h>

#define IOMUXC_GPR0	0x00
#define IOMUXC_GPR1	0x04
#define IOMUXC_GPR2	0x08
#define IOMUXC_GPR3	0x0c
#define IOMUXC_GPR4	0x10
#define IOMUXC_GPR5	0x14
#define IOMUXC_GPR6	0x18
#define IOMUXC_GPR7	0x1c
#define IOMUXC_GPR8	0x20
#define IOMUXC_GPR9	0x24
#define IOMUXC_GPR10	0x28
#define IOMUXC_GPR11	0x2c
#define IOMUXC_GPR12	0x30
#define IOMUXC_GPR13	0x34

#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK		(0x3 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x0 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7	(0x1 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK	(0x2 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 30)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK		(0x3 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED	(0x0 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR	(0x1 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR	(0x2 << 28)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK		(0x3 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED	(0x0 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7	(0x1 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK	(0x2 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK	(0x3 << 26)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK		(0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7	(0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK	(0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 24)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK		(0x3 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED	(0x0 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2	(0x1 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK	(0x2 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK	(0x3 << 22)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK		(0x3 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED	(0x0 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2	(0x1 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK	(0x2 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK	(0x3 << 20)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK		(0x3 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED	(0x0 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1	(0x1 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK	(0x2 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK	(0x3 << 18)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK		(0x3 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED	(0x0 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1	(0x1 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK	(0x2 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK	(0x3 << 16)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK		(0x3 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1	(0x0 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2	(0x1 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3	(0x2 << 14)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK		BIT(7)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF	0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX	BIT(7)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK		BIT(6)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI		0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3		BIT(6)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK		BIT(5)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4	0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2	BIT(5)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK		BIT(4)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4	0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1		BIT(4)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK		BIT(3)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2	0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1		BIT(3)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK		BIT(2)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1	0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2		BIT(2)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK		BIT(1)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1	0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3		BIT(1)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK		BIT(0)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1		0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX	BIT(0)

#define IMX6Q_GPR1_PCIE_REQ_MASK		(0x3 << 30)
#define IMX6Q_GPR1_PCIE_SW_RST			BIT(29)

Annotation

Implementation Notes