include/linux/mfd/twl4030-audio.h

Source file repositories/reference/linux-study-clean/include/linux/mfd/twl4030-audio.h

File Facts

System
Linux kernel
Corpus path
include/linux/mfd/twl4030-audio.h
Extension
.h
Size
8129 bytes
Lines
259
Domain
Core OS
Bucket
Core Kernel Interface
Inferred role
Core OS: implementation source
Status
source implementation candidate

Why This File Exists

Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __TWL4030_CODEC_H__
#define __TWL4030_CODEC_H__

/* Codec registers */
#define TWL4030_REG_CODEC_MODE		0x01
#define TWL4030_REG_OPTION		0x02
#define TWL4030_REG_UNKNOWN		0x03
#define TWL4030_REG_MICBIAS_CTL		0x04
#define TWL4030_REG_ANAMICL		0x05
#define TWL4030_REG_ANAMICR		0x06
#define TWL4030_REG_AVADC_CTL		0x07
#define TWL4030_REG_ADCMICSEL		0x08
#define TWL4030_REG_DIGMIXING		0x09
#define TWL4030_REG_ATXL1PGA		0x0A
#define TWL4030_REG_ATXR1PGA		0x0B
#define TWL4030_REG_AVTXL2PGA		0x0C
#define TWL4030_REG_AVTXR2PGA		0x0D
#define TWL4030_REG_AUDIO_IF		0x0E
#define TWL4030_REG_VOICE_IF		0x0F
#define TWL4030_REG_ARXR1PGA		0x10
#define TWL4030_REG_ARXL1PGA		0x11
#define TWL4030_REG_ARXR2PGA		0x12
#define TWL4030_REG_ARXL2PGA		0x13
#define TWL4030_REG_VRXPGA		0x14
#define TWL4030_REG_VSTPGA		0x15
#define TWL4030_REG_VRX2ARXPGA		0x16
#define TWL4030_REG_AVDAC_CTL		0x17
#define TWL4030_REG_ARX2VTXPGA		0x18
#define TWL4030_REG_ARXL1_APGA_CTL	0x19
#define TWL4030_REG_ARXR1_APGA_CTL	0x1A
#define TWL4030_REG_ARXL2_APGA_CTL	0x1B
#define TWL4030_REG_ARXR2_APGA_CTL	0x1C
#define TWL4030_REG_ATX2ARXPGA		0x1D
#define TWL4030_REG_BT_IF		0x1E
#define TWL4030_REG_BTPGA		0x1F
#define TWL4030_REG_BTSTPGA		0x20
#define TWL4030_REG_EAR_CTL		0x21
#define TWL4030_REG_HS_SEL		0x22
#define TWL4030_REG_HS_GAIN_SET		0x23
#define TWL4030_REG_HS_POPN_SET		0x24
#define TWL4030_REG_PREDL_CTL		0x25
#define TWL4030_REG_PREDR_CTL		0x26
#define TWL4030_REG_PRECKL_CTL		0x27
#define TWL4030_REG_PRECKR_CTL		0x28
#define TWL4030_REG_HFL_CTL		0x29
#define TWL4030_REG_HFR_CTL		0x2A
#define TWL4030_REG_ALC_CTL		0x2B
#define TWL4030_REG_ALC_SET1		0x2C
#define TWL4030_REG_ALC_SET2		0x2D
#define TWL4030_REG_BOOST_CTL		0x2E
#define TWL4030_REG_SOFTVOL_CTL		0x2F
#define TWL4030_REG_DTMF_FREQSEL	0x30
#define TWL4030_REG_DTMF_TONEXT1H	0x31
#define TWL4030_REG_DTMF_TONEXT1L	0x32
#define TWL4030_REG_DTMF_TONEXT2H	0x33
#define TWL4030_REG_DTMF_TONEXT2L	0x34
#define TWL4030_REG_DTMF_TONOFF		0x35
#define TWL4030_REG_DTMF_WANONOFF	0x36
#define TWL4030_REG_I2S_RX_SCRAMBLE_H	0x37
#define TWL4030_REG_I2S_RX_SCRAMBLE_M	0x38
#define TWL4030_REG_I2S_RX_SCRAMBLE_L	0x39
#define TWL4030_REG_APLL_CTL		0x3A
#define TWL4030_REG_DTMF_CTL		0x3B
#define TWL4030_REG_DTMF_PGA_CTL2	0x3C
#define TWL4030_REG_DTMF_PGA_CTL1	0x3D
#define TWL4030_REG_MISC_SET_1		0x3E
#define TWL4030_REG_PCMBTMUX		0x3F
#define TWL4030_REG_RX_PATH_SEL		0x43
#define TWL4030_REG_VDL_APGA_CTL	0x44
#define TWL4030_REG_VIBRA_CTL		0x45
#define TWL4030_REG_VIBRA_SET		0x46
#define TWL4030_REG_VIBRA_PWM_SET	0x47
#define TWL4030_REG_ANAMIC_GAIN		0x48
#define TWL4030_REG_MISC_SET_2		0x49

/* Bitfield Definitions */

/* TWL4030_CODEC_MODE (0x01) Fields */
#define TWL4030_APLL_RATE		0xF0
#define TWL4030_APLL_RATE_8000		0x00
#define TWL4030_APLL_RATE_11025		0x10
#define TWL4030_APLL_RATE_12000		0x20
#define TWL4030_APLL_RATE_16000		0x40
#define TWL4030_APLL_RATE_22050		0x50
#define TWL4030_APLL_RATE_24000		0x60
#define TWL4030_APLL_RATE_32000		0x80
#define TWL4030_APLL_RATE_44100		0x90
#define TWL4030_APLL_RATE_48000		0xA0
#define TWL4030_APLL_RATE_96000		0xE0
#define TWL4030_SEL_16K			0x08

Annotation

Implementation Notes