include/linux/mfd/ucb1x00.h
Source file repositories/reference/linux-study-clean/include/linux/mfd/ucb1x00.h
File Facts
- System
- Linux kernel
- Corpus path
include/linux/mfd/ucb1x00.h- Extension
.h- Size
- 6590 bytes
- Lines
- 259
- Domain
- Core OS
- Bucket
- Core Kernel Interface
- Inferred role
- Core OS: implementation source
- Status
- source implementation candidate
Why This File Exists
Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/device.hlinux/mfd/mcp.hlinux/gpio.hlinux/gpio/driver.hlinux/mutex.h
Detected Declarations
struct ucb1x00_plat_datastruct ucb1x00struct ucb1x00_driverstruct ucb1x00_devstruct ucb1x00_driverenum ucb1x00_resetfunction ucb1x00_clkratefunction ucb1x00_enablefunction ucb1x00_disablefunction ucb1x00_reg_writefunction ucb1x00_reg_readfunction ucb1x00_set_audio_divisorfunction ucb1x00_set_telecom_divisor
Annotated Snippet
struct ucb1x00_plat_data {
void (*reset)(enum ucb1x00_reset);
unsigned irq_base;
int gpio_base;
unsigned can_wakeup;
};
struct ucb1x00 {
raw_spinlock_t irq_lock;
struct mcp *mcp;
unsigned int irq;
int irq_base;
struct mutex adc_mutex;
spinlock_t io_lock;
u16 id;
u16 io_dir;
u16 io_out;
u16 adc_cr;
u16 irq_fal_enbl;
u16 irq_ris_enbl;
u16 irq_mask;
u16 irq_wake;
struct device dev;
struct list_head node;
struct list_head devs;
struct gpio_chip gpio;
};
struct ucb1x00_driver;
struct ucb1x00_dev {
struct list_head dev_node;
struct list_head drv_node;
struct ucb1x00 *ucb;
struct ucb1x00_driver *drv;
void *priv;
};
struct ucb1x00_driver {
struct list_head node;
struct list_head devs;
int (*add)(struct ucb1x00_dev *dev);
void (*remove)(struct ucb1x00_dev *dev);
int (*suspend)(struct ucb1x00_dev *dev);
int (*resume)(struct ucb1x00_dev *dev);
};
#define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
int ucb1x00_register_driver(struct ucb1x00_driver *);
void ucb1x00_unregister_driver(struct ucb1x00_driver *);
/**
* ucb1x00_clkrate - return the UCB1x00 SIB clock rate
* @ucb: UCB1x00 structure describing chip
*
* Return the SIB clock rate in Hz.
*/
static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
{
return mcp_get_sclk_rate(ucb->mcp);
}
/**
* ucb1x00_enable - enable the UCB1x00 SIB clock
* @ucb: UCB1x00 structure describing chip
*
* Enable the SIB clock. This can be called multiple times.
*/
static inline void ucb1x00_enable(struct ucb1x00 *ucb)
{
mcp_enable(ucb->mcp);
}
/**
* ucb1x00_disable - disable the UCB1x00 SIB clock
* @ucb: UCB1x00 structure describing chip
*
* Disable the SIB clock. The SIB clock will only be disabled
* when the number of ucb1x00_enable calls match the number of
* ucb1x00_disable calls.
*/
static inline void ucb1x00_disable(struct ucb1x00 *ucb)
{
mcp_disable(ucb->mcp);
}
/**
* ucb1x00_reg_write - write a UCB1x00 register
* @ucb: UCB1x00 structure describing chip
Annotation
- Immediate include surface: `linux/device.h`, `linux/mfd/mcp.h`, `linux/gpio.h`, `linux/gpio/driver.h`, `linux/mutex.h`.
- Detected declarations: `struct ucb1x00_plat_data`, `struct ucb1x00`, `struct ucb1x00_driver`, `struct ucb1x00_dev`, `struct ucb1x00_driver`, `enum ucb1x00_reset`, `function ucb1x00_clkrate`, `function ucb1x00_enable`, `function ucb1x00_disable`, `function ucb1x00_reg_write`.
- Atlas domain: Core OS / Core Kernel Interface.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.