include/linux/pci.h
Source file repositories/reference/linux-study-clean/include/linux/pci.h
File Facts
- System
- Linux kernel
- Corpus path
include/linux/pci.h- Extension
.h- Size
- 106316 bytes
- Lines
- 2880
- Domain
- Core OS
- Bucket
- Core Kernel Interface
- Inferred role
- Core OS: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Core operating-system implementation surface: boot, tasks, memory, VFS, syscall-facing interfaces, synchronization, credentials, and isolation.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/args.hlinux/mod_devicetable.hlinux/types.hlinux/init.hlinux/ioport.hlinux/list.hlinux/compiler.hlinux/errno.hlinux/kobject.hlinux/atomic.hlinux/device.hlinux/interrupt.hlinux/io.hlinux/resource_ext.hlinux/msi_api.huapi/linux/pci.hlinux/pci_ids.hlinux/dmapool.hasm/pci.hlinux/dma-mapping.h
Detected Declarations
struct pci_slotstruct pci_vpdstruct irq_affinitystruct pcie_bwctrl_datastruct pcie_link_statestruct pci_sriovstruct pci_p2pdmastruct rcec_eastruct pci_devstruct pci_host_bridgestruct pci_busstruct pci_opsstruct pci_bus_regionstruct pci_dynidsstruct pci_error_handlersstruct modulestruct pci_driverstruct msix_entrystruct pcie_ptm_opsstruct pci_ptm_debugfsstruct pci_fixupstruct device_nodestruct irq_domainenum pci_mmap_stateenum pci_interrupt_pinenum pcie_reset_stateenum pci_dev_flagsenum pci_irq_reroute_variantenum pci_bus_flagsenum pcie_link_widthenum pci_bus_speedenum pci_ers_resultenum pcie_bus_config_typesenum pci_fixup_passfunction pci_channel_offlinefunction pci_dev_idfunction rootfunction pci_is_bridgefunction resourcesfunction pci_is_displayfunction pcie_is_cxlfunction pci_dev_msi_enabledfunction pci_dev_msi_enabledfunction pcibios_err_to_errnofunction pci_bus_region_sizefunction pci_set_flagsfunction pci_add_flagsfunction pci_clear_flags
Annotated Snippet
struct pci_driver *driver; /* Driver bound to this device */
u64 dma_mask; /* Mask of the bits of bus address this
device implements. Normally this is
0xffffffff. You only need to change
this if your device has broken DMA
or supports 64-bit transfers. */
u64 msi_addr_mask; /* Mask of the bits of bus address for
MSI that this device implements.
Normally set based on device
capabilities. You only need to
change this if your device claims
to support 64-bit MSI but implements
fewer than 64 address bits. */
struct device_dma_parameters dma_parms;
pci_power_t current_state; /* Current operating state. In ACPI,
this is D0-D3, D0 being fully
functional, and D3 being off. */
u8 pm_cap; /* PM capability offset */
unsigned int pme_support:5; /* Bitmask of states from which PME#
can be generated */
unsigned int pme_poll:1; /* Poll device's PME status bit */
unsigned int pinned:1; /* Whether this dev is pinned */
unsigned int config_rrs_sv:1; /* Config RRS software visibility */
unsigned int imm_ready:1; /* Supports Immediate Readiness */
unsigned int d1_support:1; /* Low power state D1 is supported */
unsigned int d2_support:1; /* Low power state D2 is supported */
unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
unsigned int no_d3cold:1; /* D3cold is forbidden */
unsigned int bridge_d3:1; /* Allow D3 for bridge */
unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
unsigned int mmio_always_on:1; /* Disallow turning off io/mem
decoding during BAR sizing */
unsigned int wakeup_prepared:1;
unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
unsigned int ignore_hotplug:1; /* Ignore hotplug events */
unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
controlled exclusively by
user sysfs */
unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
bit manually */
unsigned int no_bw_notif:1; /* BW notifications may cause issues */
unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
u16 l1ss; /* L1SS Capability pointer */
#ifdef CONFIG_PCIEASPM
struct pcie_link_state *link_state; /* ASPM link state */
unsigned int aspm_l0s_support:1; /* ASPM L0s support */
unsigned int aspm_l1_support:1; /* ASPM L1 support */
unsigned int ltr_path:1; /* Latency Tolerance Reporting
supported from root to here */
#endif
unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=not supported */
pci_channel_state_t error_state; /* Current connectivity state */
struct device dev; /* Generic device interface */
int cfg_size; /* Size of config space */
/*
* Instead of touching interrupt line and base address registers
* directly, use the values stored here. They might be different!
*/
unsigned int irq;
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
unsigned int transparent:1; /* Subtractive decode bridge */
unsigned int io_window:1; /* Bridge has I/O window */
unsigned int pref_window:1; /* Bridge has pref mem window */
unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
unsigned int multifunction:1; /* Multi-function device */
unsigned int is_busmaster:1; /* Is busmaster */
unsigned int no_msi:1; /* May not use MSI */
unsigned int block_cfg_access:1; /* Config space access blocked */
unsigned int broken_parity_status:1; /* Generates false positive parity */
unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
unsigned int msi_enabled:1;
unsigned int msix_enabled:1;
unsigned int ari_enabled:1; /* ARI forwarding */
unsigned int ats_enabled:1; /* Address Translation Svc */
unsigned int pasid_enabled:1; /* Process Address Space ID */
unsigned int pri_enabled:1; /* Page Request Interface */
unsigned int tph_enabled:1; /* TLP Processing Hints */
unsigned int fm_enabled:1; /* Flit Mode (segment captured) */
unsigned int is_managed:1; /* Managed via devres */
Annotation
- Immediate include surface: `linux/args.h`, `linux/mod_devicetable.h`, `linux/types.h`, `linux/init.h`, `linux/ioport.h`, `linux/list.h`, `linux/compiler.h`, `linux/errno.h`.
- Detected declarations: `struct pci_slot`, `struct pci_vpd`, `struct irq_affinity`, `struct pcie_bwctrl_data`, `struct pcie_link_state`, `struct pci_sriov`, `struct pci_p2pdma`, `struct rcec_ea`, `struct pci_dev`, `struct pci_host_bridge`.
- Atlas domain: Core OS / Core Kernel Interface.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.